Method of manufacturing a semiconductor device including through silicon plugs

• US 10,049,931 B2
• Filed: 03/14/2016
• Issued: 08/14/2018
• Est. Priority Date: 04/05/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Hung-Pin, Lin, Yung-Chi, Yu, Chia-Lin, Hung, Jui-Pin, Hwang, Chien Ling
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US15/069,474
• Publication Number:
  US 20160197014A1
• Time in Patent Office: 883 Days
• Field of Search: 438 26
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32506 comprising an eutectic alloy
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/005 : Processes
• CPC Class Codes: H01L 33/0054 : for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/641 : characterized by the materials
• CPC Class Codes: H01L 33/644 : in intimate contact or integrated with parts of the device other than the semiconductor body
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first opening, a second opening, and a third opening in a first surface of a substrate, wherein a first region of the substrate having the first surface interposes the first and second openings and a second region of the substrate interposes the second and third openings;

forming a conductive material in the first opening and in the second opening and over the first surface in the first region of the substrate and forming the conductive material in the third opening while a photoresist feature is disposed on the second region;

reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening, the conductive material in the second opening, and the conductive material in the third opening; and

connecting a light emitting diode (LED) device to a metal pad on the third surface of the substrate.

2. A method of making a semiconductor device, the method comprising:

providing a substrate having a first surface and a second surface opposing the first surface;

etching the first surface of a substrate to form a first opening and a second opening and a third opening;

forming a first patterned photoresist layer over the first surface of the substrate, wherein a first feature of the first patterned photoresist layer is disposed on the first surface between a first opening and the third opening;

forming a conductive material in the first opening, the second opening, and the third opening, wherein each of the first, second, and third openings having conductive material with a first end adjacent the first surface of the substrate and a second end opposing end, wherein the first end of the conductive material in the first opening is connected to the first end of the conductive material in the second opening by a portion of the conductive material that is disposed on the first surface of the substrate and wherein the first feature interposes the first end of the conductive material in the first opening and the first end of the conductive material in the third opening;

removing the first feature to form a space over the first surface of the substrate;

forming a first metal pad over the second surface of the substrate, wherein the first metal pad is electrically connected to the conductive material in the first opening and the conductive material in the second opening; and

bonding a device to the first metal pad.

3. The method of claim 2, wherein etching the substrate to form the first opening and the second opening comprises forming the first opening as a circular shape and forming a second opening as a ring shape surrounding and concentric with the first opening.

4. The method of claim 2, wherein etching the substrate to form the first opening and the second opening comprises forming two adjacent double-sided comb shapes.

5. The method of claim 2, wherein etching the substrate to form the first opening and the second opening comprises forming two adjacent rectangular shape openings.

6. The method of claim 2, wherein the forming the first metal pad includes forming a seed layer directly on the second end of the conductive material in each of the first and second openings.

7. The method of claim 2,

wherein the forming the conductive material in the third opening provides the conductive material in the third opening electrically isolated from the conductive material in the first and second openings.

8. The method of claim 2, further comprising:

depositing a glue layer filling the space.

9. The method of claim 8, wherein the glue layer extends over the portion of the conductive material that is connects the first end of the conductive material in the first opening to the first end of the conductive material in the second opening.

10. The method of claim 2, further comprising:

forming a second metal pad over the second surface of the substrate and electrically connected to the conductive material of the third opening.

11. The method of claim 10, further comprising:

forming a wire extending from the device to the second metal pad.

12. The method of claim 10, the method further comprising forming a second photoresist feature interposing the first metal pad and the second metal pad;

and removing the second photoresist feature before bonding the device to the first metal pad.

13. The method of claim 2, further comprising:

forming an isolation layer and a barrier/seed layer along sidewalls of the first opening, the second opening, and the third opening prior to the forming the conductive material.

14. The method of claim 13, wherein the first feature is disposed over the isolation layer and the barrier/seed layer.

15. The method of claim 6, wherein the forming the first metal pad further includes forming the seed layer directly on the second end of the conductive material in the third opening.

16. The method of claim 15, wherein the forming the seed layer includes forming a contiguous seed layer extending over the second end of the conductive material in each of the first, second and third openings.

17. A method of making a semiconductor device, the method comprising:

providing a substrate having a first surface and an opposing second surface;

etching the first surface of a substrate to form a first opening, a second opening and a third opening, wherein the first opening interposes the second and third openings;

forming a first photoresist feature over the first surface between a first opening and the third opening;

forming a conductive material in the first opening, the second opening, and the third opening, wherein each of the first, second, and third openings having conductive material with a first end adjacent the first surface of the substrate and a second end opposing end, wherein the first end of the conductive material in the first opening is connected to the first end of the conductive material in the second opening by a portion of the conductive material that is disposed on the first surface of the substrate and wherein the first photoresist feature interposes the first end of the conductive material in the first opening and the first end of the conductive material in the third opening, the conductive material in the third opening being electrically isolated from the conductive material in the first opening;

forming a first metal pad over the second surface of the substrate, wherein the first metal pad is electrically connected to the conductive material in the first opening and the conductive material in the second opening;

forming a second metal pad over the second surface of the substrate; and

bonding an light emitted diode device to the first metal pad.

18. The method of claim 17, wherein the forming the conductive material includes copper.

19. The method of claim 17, further comprising depositing a seed layer prior to the conductive material in the first, second, and third openings.

20. The method of claim 19, wherein the first photoresist feature is formed over the seed layer.