Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units

• US 10,049,964 B2
• Filed: 10/23/2013
• Issued: 08/14/2018
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Shim, Il Kwon, Lin, Yaojian, Marimuthu, Pandi C., Chen, Kang, Gu, Yu
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US14/061,244
• Publication Number:
  US 20140048906A1
• Time in Patent Office: 1,756 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24155 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

Claims

1. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a plurality of modular interconnect units by,

(a) providing a core substrate,

(b) forming a plurality of vertical interconnects through the core substrate,

(c) forming a first insulating layer over the core substrate and vertical interconnects, and

(d) forming a plurality of openings in the first insulating layer extending to the vertical interconnects;

after forming the modular interconnect units, disposing the modular interconnect units in a peripheral region around the first semiconductor die, wherein a height of the modular interconnect units is less than a height of the first semiconductor die;

depositing an encapsulant over the first insulating layer and around the first semiconductor die;

forming a plurality of openings into a surface of the encapsulant aligned with the openings in the first insulating layer and extending to the vertical interconnects;

providing a prefabricated interposer including a second insulating layer and a conductive layer embedded within the second insulating layer and extending through the prefabricated interposer;

disposing the prefabricated interposer over the first semiconductor die and modular interconnect units; and

bonding the prefabricated interposer to the modular interconnect units with a plurality of interconnect structures contacting the conductive layer and further extending into the openings of the encapsulant to contact the vertical interconnects.

2. The method of claim 1, further including disposing a second semiconductor die over a surface of the prefabricated interposer opposite the first semiconductor die.

3. The method of claim 1, wherein the interconnect structure includes a conductive pillar or stud bump.

4. The method of claim 1, further including forming the opening in the first insulating layer extending to the vertical interconnects by laser direct ablation.

5. The method of claim 1, further including disposing an adhesive over the first semiconductor die.

6. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a plurality of modular interconnect units by,

(a) providing a core substrate,

(b) forming a plurality of vertical interconnects through the core substrate, and

(c) forming a first insulating layer over the core substrate and vertical interconnects;

after forming the modular interconnect units, disposing the modular interconnect units around the first semiconductor die;

depositing an encapsulant over the first insulating layer and around the first semiconductor die;

forming a plurality of openings into a surface of the encapsulant and extending to the vertical interconnects of the modular interconnect units;

providing a prefabricated interconnect interposer including a second insulating layer and a conductive layer embedded within the second insulating layer and extending through the prefabricated interconnect interposer; and

bonding the prefabricated interconnect interposer to the modular interconnect units with a plurality of interconnect structures contacting the conductive layer of the prefabricated interconnect interposer and further extending into the openings of the encapsulant to contact the vertical interconnects of the modular interconnect units.

7. The method of claim 6, further including disposing a second semiconductor die over the prefabricated interconnect interposer.

8. The method of claim 6, further including forming the modular interconnect units by

forming a plurality of openings in the first insulating layer extending to the vertical interconnects.

9. The method of claim 6, further including disposing an underfill material between the prefabricated interconnect interposer and semiconductor package.

10. The method of claim 6, wherein a height of the modular interconnect units is less than a height of the first semiconductor die.

11. The method of claim 6, further including planarizing the encapsulant.

12. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

providing a modular interconnect unit including a core substrate and a plurality of vertical interconnects formed through the core substrate and a first insulating layer formed over the core substrate and vertical interconnects;

disposing the modular interconnect unit adjacent to the first semiconductor die;

depositing an encapsulant over the first insulating layer of the modular interconnect unit and around the first semiconductor die;

forming an opening into a surface of the encapsulant and extending to the vertical interconnects of the modular interconnect unit;

providing an interconnect interposer including a second insulating layer and a conductive layer embedded within the second insulating layer and extending through the interconnect interposer;

disposing the interconnect interposer over the first semiconductor die and modular interconnect unit; and

bonding the interconnect interposer to the modular interconnect unit with a first interconnect structure contacting the conductive layer and extending into the opening of the encapsulant to contact the vertical interconnects of the modular interconnect unit.

13. The method of claim 12, further including disposing a second semiconductor die over the interconnect interposer.

14. The method of claim 12, wherein the first interconnect structure includes a stud bump, a conductive paste, or a conductive pillar.

15. The method of claim 12, further including forming a second interconnect structure over a surface of the modular interconnect unit opposite the first interconnect structure.

16. The method of claim 12, wherein a height of the modular interconnect units is less than a height of the first semiconductor die.

17. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a modular interconnect unit by,

(a) providing a core substrate,

(b) forming a plurality of vertical interconnects through the core substrate, and

(c) forming a first insulating layer over the core substrate and vertical interconnects;

disposing the modular interconnect unit adjacent to the first semiconductor die;

depositing an encapsulant over the first insulating layer of the modular interconnect unit and around the first semiconductor die;

forming a plurality of openings into a surface of the encapsulant and extending to the vertical interconnects of the modular interconnect unit;

disposing an interconnect interposer over the first semiconductor die and modular interconnect unit, wherein the interconnect interposer includes a second insulating layer and a conductive layer embedded within the second insulating layer and extending through the interconnect interposer; and

bonding the interconnect interposer to the modular interconnect unit with an interconnect structure contacting the conductive layer and extending into the openings of the encapsulant to contact the vertical interconnects of the modular interconnect unit.

18. The method of claim 17, further including disposing a second semiconductor die over the interconnect interposer.

19. The method of claim 17, further including forming an underfill between the interconnect interposer and first semiconductor die.

20. The method of claim 17, further including singulating through the modular interconnect unit after disposing the interconnect interposer disposed over the first semiconductor die and modular interconnect unit.

21. The method of claim 17, further including forming the modular interconnect unit by

forming an opening in the second insulating layer extending to the vertical interconnects.

22. The method of claim 17, wherein a height of the modular interconnect units is less than a height of the first semiconductor die.