Semiconductor non-volatile DRAM (NVDRAM) device

• US 10,050,040 B2
• Filed: 09/19/2017
• Issued: 08/14/2018
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yamakoshi, Hideaki
• Primary Examiner(s): Ojha, Ajay
• Application Number:
  US15/709,125
• Publication Number:
  US 20180090501A1
• Time in Patent Office: 329 Days
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM cell that holds information at a storage node, a nonvolatile memory cell, and a transistor. The nonvolatile memory cell holds information by use of the first threshold voltage as an erase state and the second threshold voltage as a write state, and shifts to the write state by a write voltage being applied in the erase state. The transistor selects whether or not to apply the write voltage (voltage of a write voltage line) to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.

Claims

1. A semiconductor device comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of memory cells coupled to the word lines and the bit lines,

wherein each of the memory cells comprises;

a DRAM cell including a capacitor to hold information at a storage node and a first control transistor;

a nonvolatile memory cell to hold information by use of a first threshold voltage as an erase state and a second threshold voltage as a write state, and to shift to the write state by a write voltage being applied in the erase state; and

a first transistor to select whether or not to apply the write voltage to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.

2. The semiconductor device according to claim 1 further comprising:

a write voltage line to which the write voltage is applied,

wherein each of the memory cells further comprises;

a resistive element coupled between a gate of the nonvolatile memory cell and the write voltage line and having a value of resistance higher than on-resistance of the first transistor, and

wherein the first transistor is coupled between the gate of the nonvolatile memory cell and a reference supply voltage, and ON/OFF of the first transistor is controlled by the voltage level at the storage node.

3. The semiconductor device according to claim 1 further comprising:

a write-back control line,

wherein each of the memory cells further comprises;

a second transistor coupled between the storage node and the nonvolatile memory cell and to write back information read from the nonvolatile memory cell to the storage node in response to activation of the write-back control line.

4. The semiconductor device according to claim 1 further comprising:

a write-back control line,

wherein each of the memory cells further comprises;

a second control transistor having one end coupled to a bit line shared by the DRAM cell, and controlled to an ON state in response to activation of a word line shared by the DRAM cell; and

a second transistor coupled between the other end of the second control transistor and the nonvolatile memory cell and to transmit information read from the nonvolatile memory cell to the second control transistor in response to activation of the write-back control line.

5. A semiconductor device supplied with a low-potential-side power supply voltage and a high-potential-side power supply voltage, the semiconductor device comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells coupled to the word lines and the bit lines; and

a write-back control line,

wherein each of the memory cells comprises;

a DRAM cell including a capacitor to hold information at a storage node and a first control transistor to couple a predetermined bit line to the storage node in response to activation of a predetermined word line;

a nonvolatile memory cell to hold information by use of a first threshold voltage as an erase state and a second threshold voltage as a write state, and to shift to the write state by a write voltage being applied in the erase state;

a first transistor to select whether or not to apply the write voltage to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell; and

a second transistor coupled between the storage node and the nonvolatile memory cell and to write back information read from the nonvolatile memory cell to the storage node in response to activation of the write-back control line.

6. The semiconductor device according to claim 5 further comprising:

a write voltage line to which the write voltage is applied; and

a terminal control line coupled to one of the source and the drain of the nonvolatile memory cell,

wherein each of the memory cells further comprises;

a resistive element coupled between a gate of the nonvolatile memory cell and the write voltage line and having a value of resistance higher than on-resistance of the first transistor, and

wherein the first transistor is coupled between a gate of the nonvolatile memory cell and the low-potential-side power supply voltage, and ON/OFF of the first transistor is controlled by a voltage level at the storage node.

7. The semiconductor device according to claim 6,

wherein each of the memory cells further comprises:

an amplifier circuit provided between the other of the source and the drain of the nonvolatile memory cell and the second transistor, and to output a voltage corresponding to the level of ‘

1’

or ‘

0’

of the storage node, according to whether a read current flows through the nonvolatile memory cell.

8. The semiconductor device according to claim 6 further comprising:

a gate control line to which an erase voltage is applied to shift the nonvolatile memory cell to the erase state,

wherein each of the memory cells further comprises;

a third transistor coupled between a gate of the nonvolatile memory cell and the gate control line, and controlled to an ON state when shifting the nonvolatile memory cell to the erase state.

9. The semiconductor device according to claim 8,

wherein the third transistor is a diode-connected transistor with an anode on the side of the gate of the nonvolatile memory cell and a cathode on the side of the gate control line.

10. The semiconductor device according to claim 8,

wherein each of the memory cells further comprises:

a diode coupled between a gate of the nonvolatile memory cell and the first transistor and having an anode on the side of the gate of the nonvolatile memory cell and a cathode on the side of the first transistor.

11. The semiconductor device according to claim 8,

wherein when reading information from the nonvolatile memory cell, the semiconductor device applies the low-potential-side power supply voltage to the gate of the nonvolatile memory cell via one of the write voltage line and the gate control line, and applies a predetermined read voltage to the terminal control line.

12. A semiconductor device supplied with a low-potential-side power supply voltage and a high-potential-side power supply voltage, the semiconductor device comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of sense amplifier circuits coupled to the bit lines and to amplify voltages of the bit lines;

a plurality of memory cells coupled to the word lines and the bit lines; and

a write-back control line,

wherein each of the memory cells comprises;

a DRAM cell including a capacitor to hold information at a storage node and a first control transistor to couple a predetermined bit line to the storage node in response to activation of a predetermined word line;

a nonvolatile memory cell to hold information by use of a first threshold voltage as an erase state and a second threshold voltage as a write state, and to shift to the write state by a write voltage being applied in the erase state;

a first transistor to select whether or not to apply the write voltage to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell;

a second control transistor having one end coupled to the predetermined bit line, and controlled to an ON state in response to activation of the predetermined word line; and

a second transistor coupled between the other end of the second control transistor and the nonvolatile memory cell and to transmit information read from the nonvolatile memory cell to the second control transistor in response to activation of the write-back control line.

13. The semiconductor device according to claim 12,

wherein when performing a refresh operation to the predetermined word line, the semiconductor device transmits information read from the nonvolatile memory cell to the predetermined bit line via the second transistor and the second control transistor, and writes back the information to the storage node via the sense amplifier circuit of the predetermined bit line.

14. The semiconductor device according to claim 12 further comprising:

a write voltage line to which the write voltage is applied; and

a terminal control line coupled to one of the source and the drain of the nonvolatile memory cell,

wherein each of the memory cells further comprises;

a resistive element coupled between a gate of the nonvolatile memory cell and the write voltage line and having a value of resistance higher than on-resistance of the first transistor, and

wherein the first transistor is coupled between a gate of the nonvolatile memory cell and the low-potential-side power supply voltage, and ON/OFF of the first transistor is controlled by a voltage level at the storage node.

15. The semiconductor device according to claim 14 further comprising:

a gate control line to which an erase voltage is applied to shift the nonvolatile memory cell to the erase state,

wherein each of the memory cells further comprises;

a third transistor coupled between a gate of the nonvolatile memory cell and the gate control line, and controlled to an ON state when shifting the nonvolatile memory cell to the erase state.

16. The semiconductor device according to claim 15,

wherein each of the memory cells further comprises:

a diode coupled between a gate of the nonvolatile memory cell and the first transistor and having an anode on the side of the gate of the nonvolatile memory cell and a cathode on the side of the first transistor.

17. The semiconductor device according to claim 15,

wherein when reading information from the nonvolatile memory cell, the semiconductor device applies the low-potential-side power supply voltage to the gate of the nonvolatile memory cell via one of the write voltage line and the gate control line, and applies the predetermined read voltage to the terminal control line.