SRAM cell with balanced write port

• US 10,050,045 B1
• Filed: 06/16/2017
• Issued: 08/14/2018
• Est. Priority Date: 06/16/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Kuo-Hsiu, Lin, Yu-Kuan, Chang, Feng-Ming, Hung, Lien Jung, Wang, Ping-Wei
• Primary Examiner(s): Junge, Bryan
• Application Number:
  US15/625,490
• Time in Patent Office: 424 Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

Claims

1. A semiconductor device, comprising:

first, second, third, fourth, and fifth active regions arranged in order from first to fifth along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors;

first, second, third, fourth, fifth, and sixth gates oriented along the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first and second gates are electrically connected, and the third and fourth gates are electrically connected;

one or more first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate; and

one or more second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

2. The semiconductor device of claim 1, wherein each of the first through fifth active regions comprises a fin, and each of the first through sixth transistors is a FinFET.

3. The semiconductor device of claim 1, wherein the first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite to the first conductivity type, and the fifth and sixth transistors are of a same conductivity type.

4. The semiconductor device of claim 1, wherein the first active region further comprises a channel region and S/D regions of a seventh transistor, and the fourth active region further comprises a channel region and S/D regions of an eighth transistor.

5. The semiconductor device of claim 4, further comprising seventh and eighth gates, wherein the seventh and eighth gates are configured to engage the channel regions of the seventh and eighth transistors respectively.

6. The semiconductor device of claim 1, wherein the one or more second conductive features comprise:

an S/D contact feature disposed over the S/D region of the fourth transistor; and

a butted contact connecting the S/D contact feature to the fifth gate.

7. The semiconductor device of claim 6, wherein the S/D contact feature is also disposed over the S/D region of the third transistor.

8. The semiconductor device of claim 1, wherein the one or more second conductive features comprise:

an S/D contact feature disposed over the S/D region of the fourth transistor; and

a conductive feature electrically connecting the S/D contact feature to at least a lower portion of the fifth gate.

9. The semiconductor device of claim 1, wherein the one or more second conductive features comprise:

an S/D contact feature disposed over the S/D region of the fourth transistor;

a first plug disposed over the S/D contact feature;

a second plug disposed over the fifth gate; and

a conductive wire connecting the first and second plugs.

10. The semiconductor device of claim 1, wherein the first, second, and sixth gates are arranged along a straight line, and the third, fourth, and fifth gates are arranged along another straight line.

11. The semiconductor device of claim 1, wherein the first, second, and fifth gates are arranged along a straight line, and the third, fourth, and sixth gates are arranged along another straight line.

12. A semiconductor device, comprising:

first, second, third, fourth, and fifth semiconductor fins oriented lengthwise along a first direction and arranged in order from first to fifth along a second direction perpendicular to the first direction, wherein the first, second, third, and fourth semiconductor fins comprise channel regions of first, second, third, and fourth FinFET transistors respectively, and the fifth semiconductor fin comprises channel regions of fifth and sixth FinFET transistors;

first, second, third, fourth, fifth, and sixth gate stacks oriented along the second direction, wherein the first through sixth gate stacks are disposed over the channel regions of the first through sixth transistors respectively;

a first plurality of conductive features that electrically connect a source/drain (S/D) region of the first transistor, a S/D region of the second transistor, and the third gate stack; and

a second plurality of conductive features that electrically connect the second gate stack, a S/D region of the third transistor, a S/D region of the fourth transistor, and the fifth gate stack,

wherein the first and second gate stacks are electrically coupled, the third and fourth gate stacks are electrically coupled, the first and second FinFETs are of opposite conductivity types, the third and fourth FinFETs are of opposite conductivity types, and the fifth and sixth FinFETs are of a same conductivity type.

13. The semiconductor device of claim 12, wherein the second plurality of conductive features include a shared contact disposed over the S/D region of the third FinFET, the S/D region of the fourth FinFET, and the fifth gate stack.

14. The semiconductor device of claim 13, wherein the shared contact is disposed over a top surface of the fifth gate stack.

15. The semiconductor device of claim 13, wherein the shared contact is disposed over a side and conductive portion of the fifth gate stack.

16. The semiconductor device of claim 12, wherein the second plurality of conductive features include:

a contact feature disposed over the S/D region of the fourth FinFET;

a first via disposed over the contact feature; and

a second via disposed over the fifth gate stack, wherein the first and second vias are electrically connected.

17. A semiconductor device, comprising:

first, second, third, fourth, fifth, and sixth transistors, wherein the first and fourth transistors are NMOS FET, the second and third transistors are PMOS FET, the fifth and sixth transistors are of a same conductivity type, and each of the first through sixth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region,

wherein the channel regions of the first through fifth transistors are arranged in order from first to fifth along a first direction,

wherein the gate stacks of the first, second, and fifth transistors, one of the S/D regions of the third transistor, and one of the S/D regions of the fourth transistor are electrically connected, and

wherein the gate stacks of the third and fourth transistors, one of the S/D regions of the first transistor, and one of the S/D regions of the second transistor are electrically connected.

18. The semiconductor device of claim 17, wherein the channel regions of the fifth and sixth transistors are aligned along a second direction perpendicular to the first direction.

19. The semiconductor device of claim 17, wherein the fifth and sixth transistors are PMOS FETs.

20. The semiconductor device of claim 17, wherein the first through sixth transistors are FinFETs.