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SRAM cell with balanced write port

  • US 10,050,045 B1
  • Filed: 06/16/2017
  • Issued: 08/14/2018
  • Est. Priority Date: 06/16/2017
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • first, second, third, fourth, and fifth active regions arranged in order from first to fifth along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors;

    first, second, third, fourth, fifth, and sixth gates oriented along the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first and second gates are electrically connected, and the third and fourth gates are electrically connected;

    one or more first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate; and

    one or more second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

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