Array substrate, manufacturing method thereof and display device

• US 10,050,092 B2
• Filed: 04/16/2015
• Issued: 08/14/2018
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Chen, Jiangbo, Wang, Can, Wang, Huifeng, Song, Wenfeng
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Bowen, Adam S
• Application Number:
  US14/891,796
• Publication Number:
  US 20160197128A1
• Time in Patent Office: 1,216 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H10K 2102/103 comprising indium oxides, e.g. ITO
• CPC Class Codes: H10K 50/805 Electrodes
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/805 Electrodes
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/40 Thermal treatment, e.g. annealing in the presence of a solvent vapour

Abstract

An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes a substrate (10) and first thin-film transistors (TFTs) (21) and first electrodes (40) formed on the substrate (10). The first TFT (21) includes a gate electrode (200), an active layer (202), a source electrode (205) and a drain electrode (204). The first electrode (40) is electrically connected with the drain electrode (204) of the first TFT (21), at least covers an area of the active layer (202) of the first TFT, not overlapped with the source electrode (205) and the drain electrode (204), and can absorb ultraviolet (UV) light. The array substrate can solve the problem of reducing the display performance of the display device as the performances degrade and even fail due to UV irradiation of the TFTs.

Claims

1. An array substrate, comprising a substrate, a first thin film transistor (TFT), a second TFT and a first electrode formed on the substrate, the first TFT including a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second TFT including a second gate electrode, a second active layer a second source electrode and a second drain electrode,

wherein the first electrode is electrically connected with the drain electrode of the first TFT, at least covers an area of the active layer of the first TFT, which area is not overlapped with the source electrode and the drain electrode, and is capable of absorbing ultraviolet (UV) light;

the second drain electrode of the second TFT is electrically connected with the first gate electrode of the first TFT; and

the first electrode also at least covers an area of the second active layer of the second TFT, which area is not overlapped with the second source electrode of the second TFT and the first drain electrode of the second TFT;

the first gate electrode of the first TFT is disposed at a side of the first active layer near the substrate, and the second gate electrode of the second TFT is disposed at a side of the second active layer near the substrate.

2. The array substrate according to claim 1, wherein the first electrode covers the first TFT.

3. The array substrate according to claim 1, wherein the first electrode is made from indium tin oxide (ITO), gallium zinc oxide (GZO) or indium zinc oxide (IZO).

4. The array substrate according to claim 1, wherein a thickness of the first electrode is from 30 nm to 300 nm.

5. The array substrate according to claim 1, wherein absorbance of the first electrode with respect to UV light of a wavelength less than 300 nm is not less than 90%.

6. The array substrate according to claim 1, wherein the first electrode is a cathode or an anode.

7. The array substrate according to claim 1, wherein the first electrode also covers the second TFT.

8. The array substrate according to claim 1, wherein the first active layer is made from an oxide semiconductor material.

9. The array substrate according to claim 1, further comprising a passivation layer, an emission layer (EML) and a second electrode formed on the substrate, wherein

the passivation layer is formed between the first electrode and the first TFT;

and the EML and the second electrode are formed on the first electrode in sequence.

10. A display device, comprising the array substrate according to claim 1.

11. The array substrate according to claim 1, wherein the first TFT further comprises a etch barrier layer disposed between the first source electrode/the first drain electrode of the first TFT and the first active layer of the first TFT, and the first source electrode and the first drain electrode are connected with the first active layer through via holes in the etch barrier layer.

12. A method for manufacturing an array substrate, comprising:

forming a first thin film transistor (TFT) on a substrate, including forming a first gate electrode, a first active layer, a first source electrode and a first drain electrode sequentially;

forming a second TFT on the substrate, including forming a second gate electrode, a second active layer, a second source electrode and a second drain electrode sequentially, in which the second drain electrode of the second TFT is electrically connected with the first gate electrode of the first TFT; and

forming a first electrode on the substrate provided with the first TFT, in which the first electrode is electrically connected with the first drain electrode of the first TFT, at least covers an area of the first active layer of the first TFT, which area is not overlapped with the first source electrode and the first drain electrode, and is capable of absorbing ultraviolet (UV) light;

the first electrode also at least covers an area of the second active layer of the second TFT, which area is riot overlapped with the second source electrode of the second TFT and the second drain electrode of the second TFT.

13. The manufacturing method according to claim 12, wherein the first electrode covers the first TFT.

14. The manufacturing method according to claim 12, wherein a thickness of the first electrode is from 30 nm to 300 nm.

15. The manufacturing method according to claim 12, wherein absorbance of the first electrode with respect to UV light of a wavelength less than 300 nm is not less than 90%.

16. The manufacturing method according to claim 12, wherein the first electrode also covers the second TFT.

17. The manufacturing method according to claim 12, after forming of the first TFT and the second TFT on the substrate and before forming of the first electrode, further comprising:

forming a passivation layer on the substrate.

18. The manufacturing method according to claim 12, after forming of the first electrode on the substrate provided with the first TFT, further comprising:

cleaning the substrate with UV light.

19. The manufacturing method according to claim 18, after cleaning the substrate with UV light, further comprising:

forming an EMI and a second electrode on the substrate in sequence.