Nanosheet transistors on bulk material

• US 10,050,107 B1
• Filed: 02/13/2017
• Issued: 08/14/2018
• Est. Priority Date: 02/13/2017
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Xie, Ruilong, Yamashita, Tenko, Yeh, Chun-Chen
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US15/430,764
• Publication Number:
  US 20180233557A1
• Time in Patent Office: 547 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first gate on a gate region of a starting substrate, wherein the starting substrate comprises a layered nanosheet above a buffer sacrificial layer, wherein the buffer sacrificial layer is located on a bulk substrate, and wherein the layered nanosheet comprises alternating sacrificial layers and semiconductor layers;

anisotropically etching the starting substrate in a source/drain region of the starting substrate, wherein etching the starting substrate creates a trench through the layered nanosheet and the buffer sacrificial layer and into the bulk substrate;

forming an insulating layer on the inside of the trench;

forming a masking layer over in the trench in the starting substrate, wherein a top surface of the masking layer is below a top surface of the buffer sacrificial layer and covering a portion of the insulating layer;

removing the unmasked portion of the insulating layer;

forming a source/drain in the trench; and

removing the buffer sacrificial layer and the sacrificial layers in the layered nanosheet.

2. The method of claim 1 further comprising removing a portion of the buffer sacrificial layer and a portion of the sacrificial layers in the gate region.

3. The method of claim 2, wherein forming the insulating layer on the inside of the trench comprises depositing the insulating layer on a vertical surface of the buffer sacrificial layer and a vertical surface of the sacrificial layers, and wherein the vertical surface of the buffer sacrificial layer and the vertical surface of the sacrificial layers are located in the gate region.

4. The method of claim 3, wherein removing the unmasked portion of the insulating layer comprises an anisotropic etch.

5. The method of claim 3, wherein removing the unmasked portion of the insulating layer comprises retaining the portion of the insulating layer located beneath the first gate.

6. The method of claim 1, wherein the first gate is a dummy gate.

7. The method of claim 6 further comprising:

removing the dummy gate;

removing the buffer sacrificial layer and the sacrificial layers in the gate region;

forming a gate dielectric in the gate region; and

forming a gate metal in the gate region.

8. The method of claim 1, wherein a thickness of the buffer sacrificial layer is about 50 nm and about 200 nm.

9. The method of claim 1, wherein a thickness of each of the sacrificial layers is about 4 nm and about 10 nm.

10. The method of claim 1, wherein a thickness of each of the semiconductor layers is about 4 nm and about 10 nm.

11. The method of claim 1 further comprising:

forming an inter layer dielectric (ILD) above the source/drain and above the first gate, wherein forming the ILD completely fills a region between the source/drain and the insulating layer; and

forming source/drain contacts and a gate contact through the ILD.

12. The method of claim 1 further comprising:

forming an inter layer dielectric (ILD) above the source/drain and above the first gate, wherein forming the ILD partially fills a region between the source/drain and the insulating layer; and

forming source/drain contacts and a gate contact through the ILD.

13. The method of claim 1 further comprising:

forming an inter layer dielectric (ILD) above the source/drain and above the first gate, wherein forming the ILD completely fills a region between the source/drain and the insulating layer; and

forming source/drain contacts and a gate contact through the ILD.

14. The method of claim 1 further comprising:

forming an inter layer dielectric (ILD) above the source/drain and above the first gate, wherein there is no ILD in a region between the source/drain and the insulating layer; and

forming source/drain contacts and a gate contact through the ILD.

15. The method of claim 1, wherein the sacrificial layers and the sacrificial buffer layer comprise silicon germanium.