Method of forming a polysilicon sidewall oxide region in a memory cell

• US 10,050,131 B2
• Filed: 12/11/2016
• Issued: 08/14/2018
• Est. Priority Date: 12/10/2015
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Wong, Jack, Kabeer, Sajid, Hymas, Mel, Murali, Santosh, Kopp, Brad
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US15/375,094
• Publication Number:
  US 20170170303A1
• Time in Patent Office: 611 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

Claims

1. A method of fabricating a memory cell of a semiconductor device, the method comprising:

depositing a conductive layer having a top surface and a side surface;

forming a partial ONO layer over the top surface of the conductive layer by depositing a first oxide layer on the top surface of the conductive layer and a silicon nitride layer on top of the first oxide layer, wherein the side surface of the conductive layer remains exposed; and

forming a sidewall oxide layer adjacent the side surface of the conductive layer by a process including;

depositing a high temperature oxide (HTO) film directly on the side surface of the conductive layer and on top of the silicon nitride layer thereby forming the ONO layer; and

performing a rapid thermal oxidation (RTO) anneal.

2. The method of claim 1, wherein the sidewall oxide layer is formed by depositing the HTO film on the side surface of the conductive layer and subsequently performing the RTO anneal of the deposited HTO film.

3. The method of claim 1, wherein the deposited HTO film has a thickness in a range of 50-120 Å

.

4. The method of claim 1, wherein the deposited HTO film has a thickness in a range of 60-80 Å

.

5. The method of claim 1, wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1000°

C.-1200°

C. for a duration in the range of 25-60 sec.

6. The method of claim 1, wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1050°

C.-1150°

C. for a duration in a range of 30-40 sec.

7. The method of claim 1, wherein the sidewall oxide layer is formed by performing the RTO anneal of the conductive layer and the partial ONO layer, and after the RTO anneal, depositing the HTO film over the side surface of the conductive layer.

8. The method of claim 7, wherein:

the RTO anneal oxidizes the exposed side surface of the conductive layer, and

the HTO film is deposited on the oxidized side surface of the conductive layer.

9. A method of fabricating a memory cell of a semiconductor device, the method comprising:

forming a stack structure on a wafer by;

depositing a conductive layer on a first oxide layer;

forming a second oxide layer over a top surface of the conductive layer,

forming a silicon nitride layer over the top surface of the first oxide layer, and

forming and patterning a protective photoresist layer silicon nitride layer and performing an etching down to the first oxide layer, wherein a side surface of the conductive layer remains exposed;

depositing a high temperature oxide (HTO) film immediately on the side surface of the conductive layer and on top of the silicon nitride layer; and

performing a rapid thermal oxidation (RTO) anneal.

10. The method of claim 9, wherein a sidewall oxide layer is formed by depositing the HTO film on the side surface of the conductive layer and subsequently performing the RTO anneal of the deposited HTO film.

11. The method of claim 9, wherein the deposited HTO film has a thickness in a range of 50-120 Å

.

12. The method of claim 9, wherein the deposited HTO film has a thickness in a range of 60-80 Å

.

13. The method of claim 9, wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1000°

C.-1200°

C. for a duration in the range of 25-60 sec.

14. The method of claim 9, wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1050°

C.-1150°

C. for a duration in a range of 30-40 sec.

15. The method of claim 9, wherein the second oxide layer has a thickness between 60-120 Å

and the silicon nitride layer has a thickness between 60-200 Å

.

16. The method of claim 9, wherein a sidewall oxide layer is formed by performing the RTO anneal of the stack structure, and after the RTO anneal, depositing the HTO film over the side surface of the conductive layer.

17. The method of claim 16, wherein:

the RTO anneal oxidizes the side surface of the conductive layer, and

the HTO film is deposited on the oxidized side surface of the conductive layer.

18. The method of claim 9, further comprising the step of cleaning the wafer after forming the stack structure.

19. The method of claim 9, wherein a total thickness of an oxide layer following the RTO anneal is between 50 and 120 Å

on top of the silicon nitride layer, between 100 and 500 Å

on the side surface of the conductive layer, and between 100 and 300 Å

above a substrate.