Rectifier diode

• US 10,050,140 B2
• Filed: 02/25/2014
• Issued: 08/14/2018
• Est. Priority Date: 03/18/2013
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Goerlach, Alfred
• Primary Examiner(s): CHEN, DAVID Z
• Application Number:
  US14/776,455
• Publication Number:
  US 20160056284A1
• Time in Patent Office: 1,631 Days
• Field of Search: 257328, 257329, 257330, 257471, 257481, 257E21359, 257E29257, 257E29327, 257E29338
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A pseudo-Schottky diode has an n-channel trench MOSFET which includes: a cathode, an anode, and located between the cathode and the anode, the following elements: a highly n⁺-doped silicon substrate; an n-doped epilayer having a trench extending into the n-doped epilayer from above; p-doped body regions provided above the n-doped epilayer and between the trenches. Highly n⁺-doped regions and highly p⁺-doped regions are provided on the upper surface of the p-doped body regions. Dielectric layers are provided on the side walls of the trench. The trench is filled with a first p-doped polysilicon layer, and the bottom of the trench is formed by a second p-doped layer which is in contact with the first p-doped polysilicon layer, and the second p-doped layer determines the breakdown voltage of the pseudo-Schottky diode.

Claims

1. A pseudo-Schottky diode comprising:

an n-channel trench MOSFET that includes;

a drain with a cathode metal;

an anode metal; and

located between the cathode metal and the anode metal, the following elements;

a highly n⁺-doped silicon substrate;

an n-doped epilayer having trenches extending into the n-doped epilayer from above; and

p-doped body regions provided above the n-doped epilayer and between the trenches;

wherein;

highly n⁺-doped regions forming a source of the MOSFET and highly p⁺-doped regions are provided on the upper surface of the p-doped body regions;

dielectric layers are provided on the side walls of the trenches;

with respect to at least one of the trenches;

a first p-doped layer, which is a polysilicon layer, forms a gate of the MOSFET, fills a first portion of the respective trench, and is electrically connected to the highly n⁺-doped regions and the highly p⁺-doped regions via a layer of the anode metal that extends from over the first p-doped layer to over the highly n⁺-doped regions and the highly p⁺-doped regions;

a second p-doped layer is;

in contact with an entirety of a bottom face of the first p-doped layer;

is at a bottom-most region of the respective trench;

extends to below a lowest point of that of the dielectric layers which is included in the respective trench; and

is in contact with at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate; and

a breakdown voltage of a junction between the second p-doped layer and the at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate (a) is lower than a breakdown voltage between the first p-doped layer and the n-doped epilayer and (b) thereby forms the breakdown voltage of the pseudo-Schottky diode; and

the gate, the body regions, and the source are monolithically and electrically connected to one another.

2. The pseudo-Schottky diode as recited in claim 1, wherein the second p-doped layer extends into the highly n⁺-doped silicon substrate.

3. The pseudo-Schottky diode as recited in claim 1, wherein the dielectric layers provided on the side walls each have a thickness that is at least 5 nm and less than 15 nm.

4. The pseudo-Schottky diode as recited in claim 3, wherein the threshold voltage of the pseudo-Schottky diode is less than 350 mV.

5. The pseudo-Schottky diode as recited in claim 1, wherein the bottoms of the trenches are all formed by the second p-doped layer which is in contact with the first p-doped layer of respective ones of the trenches.

6. The pseudo-Schottky diode as recited in claim 1, wherein a bottom of at least another one of the trenches is formed by an oxide layer in contact with a p-doped polysilicon layer of the respective trench that fills a part of the respective trench above the oxide layer.

7. The pseudo-Schottky diode as recited in claim 1, wherein, with respect to at least another one of the trenches, a bottom and side walls of the respective trench is formed by an oxide layer that is in contact with a p-doped polysilicon layer that fills a part of the respective trench above the portion of the oxide layer that is at the bottom of the respective trench, and the oxide layer is thicker at the bottom of the respective trench than at the side walls of the respective trench.

8. The pseudo-Schottky diode as recited in claim 1, wherein the breakdown voltage of the pseudo-Schottky diode for currents in the range of 1 mA to 100 mA is between 20 V and 50 V.

9. The pseudo-Schottky diode as recited in claim 1, wherein the cutoff voltage of the pseudo-Schottky diode is less than 0.8 V for a current flow at a current density of 500 A/cm².

10. The pseudo-Schottky diode as recited in claim 9, wherein the cutoff voltage of the pseudo-Schottky diode is between 0.5 V and 0.7 V for a current flow at a current density of 500 A/cm².

11. The pseudo-Schottky diode as recited in claim 1, wherein the pseudo-Schottky diode has a solderable front side and a solderable back side.

12. The pseudo-Schottky diode as recited in claim 1, wherein the pseudo-Schottky diode is a component of a motor vehicle generator.

13. The pseudo-Schottky diode as recited in claim 1, wherein the pseudo-Schottky diode is a component of a motor vehicle alternating current generator having more than three phases.

14. The pseudo-Schottky diode as recited in claim 1, wherein the second p-doped layer is arranged such that, if a high reverse voltage, that is above the breakdown voltage of the pseudo-Schottky diode, occurs:

the junction between the second p-doped layer and the at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate breaks down; and

no charge carrier injection can occur into the first p-doped layer without passing into the second p-doped layer.

15. The pseudo-Schottky diode as recited in claim 1, wherein the second p-doped layer is arranged such that, if a high reverse voltage, that is above the breakdown voltage of the pseudo-Schottky diode, occurs:

the junction between the second p-doped layer and the at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate breaks down;

no resulting charge carrier injection can occur into the first p-doped layer without passing into the second p-doped layer; and

no resulting charge carrier injection can occur through any dielectric layer in the at least one trench.

16. The pseudo-Schottky diode as recited in claim 1, wherein the dielectric layers provided on the side walls each has a thickness of 5 nm 30 nm.

17. A circuit comprising:

a load; and

a pseudo-Schottky diode that includes an n-channel trench MOSFET, the n-channel trench MOSFET including;

a drain, which is a cathode;

an anode; and

located between the cathode and the anode, the following elements;

a highly n⁺-doped silicon substrate;

an n-doped epilayer having trenches extending into the n-doped epilayer from above; and

p-doped body regions provided above the n-doped epilayer and between the trenches;

wherein;

highly n⁺-doped regions forming a source of the MOSFET and highly p⁺-doped regions are provided on the upper surface of the p-doped body regions;

dielectric layers are provided on the side walls of the trenches;

with respect to at least one of the trenches;

a first p-doped layer, which is a polysilicon layer, forms a gate and fills a first portion of the respective trench and is electrically connected to the highly n⁺-doped regions and the highly p⁺-doped regions via a layer of the anode that extends from over the first p-doped layer to over the highly n⁺-doped regions and the highly p⁺-doped regions;

a second p-doped layer that;

is in contact with an entirety of a bottom face of the first p-doped layer;

is at a bottom-most region of the respective trench;

extends to below a lowest point of that of the dielectric layers which is included in the respective trench; and

is in contact with at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate; and

a breakdown voltage of a junction between the second p-doped layer and the at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate (a) is lower than a breakdown voltage between the first p-doped layer and the n-doped epilayer and (b) thereby forms the breakdown voltage of the pseudo-Schottky diode; and

the gate, the body regions, and the source are monolithically and electrically connected to one another.

18. The circuit as recited in claim 17, wherein the circuit allows for a high reverse voltage above the breakdown voltage of the pseudo-Schottky diode to occur, in response to which high reverse voltage, the diode is structured such that:

the junction between the second p-doped layer and the at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate responsively breaks down; and

no charge carrier injection can occur into the first p-doped layer without passing into the second p-doped layer.

19. The circuit as recited in claim 17, wherein the circuit allows for a high reverse voltage above the breakdown voltage of the pseudo-Schottky diode to occur, in response to which high reverse voltage, the diode is structured such that:

the junction between the second p-doped layer and the at least one of the n-doped epilayer and the highly n⁺-doped silicon substrate breaks down;

no resulting charge carrier injection can occur into the first p-doped layer without passing into the second p-doped layer; and

no resulting charge carrier injection can occur through any dielectric layer in the at least one trench.

20. The circuit as recited in claim 17, wherein the pseudo-Schottky diode is a component of a motor vehicle generator of the circuit.

21. The circuit as recited in claim 17, wherein the pseudo-Schottky diode is a component of a motor vehicle alternating current generator of the circuit having more than three phases.