Second order harmonic cancellation for radio frequency front-end switches

• US 10,050,662 B2
• Filed: 07/27/2017
• Issued: 08/14/2018
• Est. Priority Date: 05/08/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Zhao, Huan, Li, Qiang
• Primary Examiner(s): West, Lewis
• Application Number:
  US15/661,774
• Publication Number:
  US 20170338852A1
• Time in Patent Office: 383 Days
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04B 2001/485 inhibiting unwanted transmission

Abstract

A radio frequency switch circuit with improved harmonic suppression and low insertion loss has an antenna port and a plurality of signal ports. A plurality of transistor switch circuits, are connected to a respective one of the plurality of signal ports and to the antenna port. Each of the transistor switch circuits has a transistor, which in an off state, together with a harmonic suppression capacitor and a parallel inductor both connected thereto, define a tank circuit that suppresses RF signals applied to the corresponding transistor switch circuit from a different one of the transistor switch circuits. The harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the transistor.

Claims

1. A radio frequency single pole, triple throw switch, comprising:

a common pole terminal;

a first signal terminal;

a first control line terminal;

a first transistor with a body, a source connected to the first signal terminal, a drain connected to the common pole terminal, and a gate connected to the first control line terminal, the first transistor being selectively activatable in response to a first enable signal applied to the first control line terminal;

a first transistor harmonic suppression capacitor connected across the body and the drain of the first transistor;

a first inductor connected in parallel to the source and the drain of the first transistor, the first inductor and the first transistor harmonic suppression capacitor defining a first tank circuit with the first transistor in a deactivated state, the first tank circuit blocking radio frequency signals on the drain of the first transistor;

a second signal terminal;

a second control line terminal;

a second transistor with a body, a source connected to the second signal terminal, a drain connected to the common pole terminal, and a gate connected to the second control line terminal, the second transistor being selectively activatable in response to a second enable signal applied to the first control line terminal;

a second transistor harmonic suppression capacitor connected across the body and the drain of the second transistor;

a second inductor connected in parallel to the source and the drain of the second transistor, the second inductor and the second harmonic suppression capacitor defining a second tank circuit with the second transistor in a deactivated state, the second tank circuit blocking radio frequency signals on the drain of the second transistor;

a third signal terminal;

a third control line terminal;

a third transistor with a body, a source connected to the third signal terminal, a drain connected to the common pole terminal, and a gate connected to the third control line terminal, the third transistor being selectively activatable in response to a third enable signal applied to the third control line terminal;

a third transistor harmonic suppression capacitor connected across the body and the drain of the third transistor; and

a third inductor connected in parallel to the source and the drain of the third transistor, the third inductor and the third harmonic suppression capacitor defining a third tank circuit with the third transistor in a deactivated state, the third tank circuit blocking radio frequency signals on the drain of the third transistor.

2. The switch of claim 1 further comprising a first transistor activation suppression capacitor connected across the gate and the source of the first transistor, a second transistor activation suppression capacitor connected across the gate and the source of the second transistor, and a third transistor activation suppression capacitor connected across the gate and the source of the third transistor.

3. The switch of claim 2 wherein each of the transistor activation suppression capacitor are tuned to maximize peak power handling capacity of the respective transistor.

4. The switch of claim 1 wherein the first harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the first transistor, the second harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the second transistor, and the third harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the third transistor.

5. The switch of claim 1 further comprising a first direct current blocking capacitor connected between the drain of the first transistor and the common pole terminal, a second direct current blocking capacitor connected between the drain of the second transistor and the common pole terminal, and a third direct current blocking capacitor connected between the drain of the third transistor and the common pole terminal.

6. The switch of claim 1 further comprising a first direct current blocking capacitor connected between the first signal terminal and the source of the first transistor, a second direct current blocking capacitor connected between the second signal terminal and the source of the second transistor, and a third direct current blocking capacitor connected between the third signal terminal and the source of the third transistor.

7. The switch of claim 1 wherein the first transistor, the second transistor, and the third transistor have an n-type metal oxide semiconductor (N-MOS) field effect structure.

8. A radio frequency single pole, triple throw switch comprising:

a common pole terminal;

first, second and third throw terminals;

first, second, and third transistors each including a source, a drain, and a gate, with the source of each of the transistors being connected to a respective one of the first, second, and third throw terminals and the drain of each of the transistors being connected to the common pole terminal;

harmonic suppression capacitors connected across the body and the drain of the corresponding one of the first, second, and third transistors; and

parallel inductors connected across the source and the drain of each of the first, second, and third transistors together with the corresponding harmonic suppression capacitors that define respective tank circuits blocking radio frequency signals on the drains of the corresponding one of the first, second, and third transistors in a deactivated state.

9. The radio frequency single pole, triple throw switch of claim 8 further comprising first, second, and third control line terminals each connected to the gate of the corresponding one of the first, second, and third transistors, each of the transistors being selectively activatable in response to an enable signal applied to the corresponding one of the first, second, and third control line terminals.

10. The radio frequency single pole, triple throw switch of claim 8 wherein each of the harmonic suppression capacitors are tuned to distribute large signal voltage swings in an input signal across parasitic diodes of the corresponding one of the first, second, and third transistors.

11. The radio frequency single pole, triple throw switch of claim 10 wherein a first one of parasitic diodes in each of the first, second, and third transistors is between the body and the drain thereof.

12. The radio frequency single pole, triple throw switch of claim 11 wherein a second one of the parasitic diodes in each of the first, second, and third transistors is between the body and the source thereof.

13. The radio frequency single pole, triple throw switch of claim 8 further comprising first, second, and third transistor activation suppression capacitors connected to a respective one of the first, second, and third transistors.

14. The radio frequency single pole, triple throw switch of claim 12 wherein the transistor activation suppression capacitors are connected across the source and the gate of the corresponding one of the first, second, and third transistors.

15. The radio frequency single pole, triple throw switch of claim 8 further comprising a direct current blocking capacitor connected to the common pole terminal.

16. The radio frequency single pole, single throw switch of claim 8 further comprising a direct current blocking capacitor connected to each of the first, second, and third throw terminals.

17. The radio frequency single pole, triple throw switch of claim 8 wherein the first, second, and third transistors each have an n-type metal oxide semiconductor (N-MOS) field effect structure.

18. A single pole, multiple throw switch comprising:

a common pole terminal;

a plurality of throw terminals;

a plurality of transistors each including a source, a drain, and a gate, with the source of each of the transistors being connected to a respective one of the throw terminals and the drain of each of the transistors being connected to the common pole terminal; and

tank circuits connected to each of the transistors blocking signals on the drains thereof in a deactivated state, each of the tank circuits including a parallel inductor connected across the source and the drain of the corresponding one of the transistors.

19. The single pole, multiple throw switch of claim 18 wherein the tank circuits each include a harmonic suppression capacitor connected to the transistor and tuned to distribute large signal voltage swings in an input signal among parasitic diodes of the corresponding one of the transistors.

20. The single pole, multiple throw switch of claim 18 further comprising a plurality of control line terminals each connected to the gate of the corresponding one of the transistors, each of the transistors being selectively activatable in response to an enable signal applied to the corresponding one of the control line terminals.