Method for performing processor resource allocation in an electronic device, and associated apparatus

• US 10,055,259 B2
• Filed: 12/14/2015
• Issued: 08/21/2018
• Est. Priority Date: 05/26/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lo, Tzu-Jen, Lin, Yu-Ming, Chen, Jia-Ming, Chang, Ya-Ting, Tang, Nicholas Ching Hui, Chen, Yin, Chou, Hung-Lin
• Primary Examiner(s): Kim, Dong
• Application Number:
  US14/967,387
• Publication Number:
  US 20160350156A1
• Time in Patent Office: 981 Days
• Field of Search: None
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

Claims

1. A method for performing processor resource allocation in an electronic device, the method comprising the steps of:

obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task, to selectively utilize a specific processor core within a plurality of processor cores to perform the task;

determining whether at least one scenario task exists within others of the plurality of tasks;

determining according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and

performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks,

wherein the task-related information comprises a queue time and an execution time, the queue time representing a time period that the task is in a queue, the execution time representing a time period for execution of the task, and

wherein the task is determined to be the heavy task in response to a derivative of the queue time and the execution time satisfying a predetermined criterion.

2. The method of claim 1, wherein the step of determining according to the application requirements the minimum processor core count and the minimum operating frequency for performing the at least one scenario task further comprises:

when the at least one scenario task exists, utilizing at least one other processor core within others of the plurality of processor cores to perform the at least one scenario task,

wherein a number of the at least one other processor core is greater than or equal to the minimum processor core count and an operating frequency of the at least one other processor core is greater than or equal to the minimum operating frequency.

3. The method of claim 1, wherein the step of obtaining the task-related information to determine whether the task of the plurality of tasks is the heavy task to selectively utilize the specific processor core within the plurality of processor cores to perform the task further comprises:

when the task is the heavy task, utilizing the specific processor core to perform the task.

4. The method of claim 3, wherein the step of obtaining the task-related information to determine whether the task of the plurality of tasks is the heavy task to selectively utilize the specific processor core within the plurality of processor cores to perform the task further comprises:

when the task is the heavy task, utilizing the specific processor core to perform the task with the specific processor core operating at a highest operating frequency thereof.

5. The method of claim 1, wherein the obtaining of the task-generated information comprises:

performing loading measurement on the task to generate a loading measurement result; and

generating the task-related information according to the loading measurement result.

6. The method of claim 5, wherein the step of obtaining the task-related information to determine whether the task of the plurality of tasks is the heavy task to selectively utilize the specific processor core within the plurality of processor cores to perform the task further comprises:

when the loading measurement result reaches a predetermined threshold, determining that the task of the plurality of tasks is the heavy task.

7. The method of claim 1, wherein the step of obtaining the task-related information to determine whether the task of the plurality of tasks is the heavy task to selectively utilize the specific processor core within the plurality of processor cores to perform the task further comprises:

when the task is the heavy task, utilizing a set of specific processor cores within the plurality of processor cores to perform a set of predefined heavy tasks, respectively, the set of specific processor cores corresponding to highest computing capability with respect to the plurality of processor cores.

8. The method of claim 1, wherein the task-related information is obtained from a program module running on the electronic device.

9. The method of claim 1, wherein the method is applied to at least one processor in the electronic device, and the at least one processor comprises the plurality of processor cores.

10. An apparatus for performing processor resource allocation in an electronic device, the apparatus comprising at least one portion of the electronic device, the apparatus comprising:

a plurality of processor cores, positioned within the electronic device, arranged for selectively performing operations for the electronic device; and

a control circuit, embedded within the plurality of processor cores or positioned outside the plurality of processor cores, arranged for obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task, to selectively utilize a specific processor core within the plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task,

wherein the control circuit performs processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks,

wherein the task-related information comprises a queue time and an execution time, the queue time representing a time period that the task is in a queue, the execution time representing a time period for execution of the task, and

wherein the task is determined to be the heavy task in response to a derivative of the queue time and the execution time satisfying a predetermined criterion.

11. The apparatus of claim 10, wherein when the at least one scenario task exists, the control circuit utilizes at least one other processor core within others of the plurality of processor cores to perform the at least one scenario task, wherein a number of the at least one other processor core is greater than or equal to the minimum processor core count and an operating frequency of the at least one other processor core is greater than or equal to the minimum operating frequency.

12. The apparatus of claim 10, wherein when the task is the heavy task, the control circuit utilizes the specific processor core to perform the task.

13. The apparatus of claim 12, wherein when the task is the heavy task, the control circuit utilizes the specific processor core to perform the task with the specific processor core operating at a highest operating frequency thereof.

14. The apparatus of claim 10, wherein, in obtaining the task-related information, the control circuit performs loading measurement on the task to generate a loading measurement result, and generates the task-related information according to the loading measurement result.

15. The apparatus of claim 14, wherein when the loading measurement result reaches a predetermined threshold, the control circuit determines that the task of the plurality of tasks is the heavy task.

16. The apparatus of claim 10, wherein when the task is the heavy task, the control circuit utilizes a set of specific processor cores within the plurality of processor cores to perform a set of predefined heavy tasks, respectively, the set of specific processor cores corresponding to highest computing capability with respect to the plurality of processor cores.

17. The apparatus of claim 10, wherein the task-related information is obtained from a program module running on the electronic device.

18. The apparatus of claim 10, wherein the apparatus comprises at least one processor in the electronic device, and the at least one processor comprises the plurality of processor cores.

19. The apparatus of claim 18, wherein the control circuit is implemented with the at least one processor having at least one program module running thereon.