Reception according to a data transfer protocol of data directed to any of a plurality of destination entities

• US 10,055,264 B2
• Filed: 03/20/2015
• Issued: 08/21/2018
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: SolarFlare Communications Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Pope, Steven Leslie, Roberts, Derek Edward, Riddoch, David James, Law, Greg, Grantham, Steve, Slattery, Matthew
• Primary Examiner(s): Park, Jeong S
• Application Number:
  US14/663,898
• Publication Number:
  US 20150201007A1
• Time in Patent Office: 1,250 Days
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/325 in the network layer [OSI layer 3], e.g. X.25 H04L69/16 takes precedence

Abstract

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

Claims

1. A data processing system comprising:

a data processor for executing instructions to support two or more processes configured to issue instructions for transmission of data to a remote receiver;

memory for storing data;

an interface whereby the data processor can transmit data to the remote receiver; and

a configuration store storing an identification of a mapping between a first area of the memory of the data processing system and a second area of a memory of the remote receiver, and an identification of a process, of the two or more processes, authorized to initiate transmission of the data in accordance with the mapping;

the interface being responsive to receiving an instruction of a predetermined form from the process, supported by the data processor specifying data in the first area of the memory, to read the specified data from the first area and transmit that data to the remote receiver together with the identification of the mapping and the identification of the process stored for the mapping in the configuration store.

2. The data processing system as claimed in claim 1, wherein the configuration store is local to the interface.

3. The data processing system as claimed in claim 1, wherein the data processor implements a plurality of queues for communication between the two or more processes and the interface, each queue being associated with a respective process, and the interface is arranged to identify which process an instruction is from by the queue on which it has received the instruction.

4. The data processing system as claimed in claim 1, wherein the interface is arranged to read the data from the area by direct memory access.

5. The interface as claimed in claim 1, wherein the interface is a network interface and is arranged to transmit the data to the receiver by means of a network protocol.

6. The interface as claimed in claim 5, wherein the network protocol is TCP/IP.

7. The interface as claimed in claim 5, wherein the interface is arranged to transmit the data over Ethernet.

8. The data processing system as claimed in claim 1, wherein the interface is arranged to write the data from the area by direct memory access.

9. The interface as claimed in claim 1, wherein the interface is a network interface and is arranged to receive the data by means of a network protocol.

10. The interface as claimed in claim 9, wherein the network protocol is TCP/IP.

11. The interface as claimed in claim 9, wherein the interface is arranged to receive the data over Ethernet.

12. The data processing system as claimed in claim 1, wherein the mapping is a mapping between a first set of buffers of the data processing system and a second set of buffers of the remote receiver;

the configuration store further comprises an identification of the first set of buffers of the data processing system; and

the first set of buffers comprises at least one buffer comprising the first area of memory, and the second set of buffers comprises at least one buffer comprising the second area of memory.

13. The data processing system as claimed in claim 12, wherein the first set of buffers comprises a plurality of buffers.

14. The data processing system as claimed in claim 12, wherein the second set of buffers comprises a plurality of buffers.

15. The data processing system as claimed in claim 12, wherein the data processor is configured to modify the identification of the first set of buffers to at least one of:

remove a buffer from the first set of buffers; and

add a buffer to the first set of buffers.

16. A data processing system comprising:

a data processor for executing instructions to support two or more processes configured to issue instructions for transmission of data to a remote receiver;

memory for storing data;

an interface whereby the data processor can receive data from a remote receiver; and

a configuration store storing an identification of a mapping between a first area of the memory of the data processing system and a second area of a memory of the remote receiver, and an identification of a process, of the two or more processes, on a remote receiver authorized to initiate transmission of the data in accordance with the mapping;

the interface being responsive to receiving, from the remote receiver, data directed to the first area of the memory together with an identification of a process, to check whether that identified process matches the identification of the process stored for the mapping in the configuration store and only if it does match to write that data to the first area of the memory.

17. The data processing system as claimed in claim 16, wherein the configuration store is local to the interface.

18. The data processing system as claimed in claim 16, wherein the interface is arranged to write the data from the area by direct memory access.

19. The interface as claimed in claim 16, wherein the interface is a network interface and is arranged to receive the data by means of a network protocol.

20. The interface as claimed in claim 16, wherein the interface is arranged to receive the data over Ethernet.

21. The data processing system as claimed in claim 16, wherein the mapping is a mapping between a first set of buffers of the data processing system and a second set of buffers of the remote receiver;

the configuration store further comprises an identification of the first set of buffers of the data processing system; and

the first set of buffers comprises at least one buffer comprising the first area of memory, and the second set of buffers comprises at least one buffer comprising the second area of memory.

22. The data processing system as claimed in claim 21, wherein the first set of buffers comprises a plurality of buffers.

23. The data processing system as claimed in claim 21, wherein the second set of buffers comprises a plurality of buffers.

24. The data processing system as claimed in claim 21, wherein the data processor is configured to modify the identification of the first set of buffers to at least one of:

remove a buffer from the first set of buffers; and

add a buffer to the first set of buffers.