Memory storage windows in a memory system

• US 10,055,343 B2
• Filed: 12/19/2016
• Issued: 08/21/2018
• Est. Priority Date: 12/29/2015
• Status: Active Grant

• Current Assignee: Memory Technologies LLC (Pendrell Corporation)
• Original Assignee: Memory Technologies LLC (Pendrell Corporation)
• Inventors: Mylly, Kimmo J., Hyvonen, Jani
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US15/383,765
• Publication Number:
  US 20170185510A1
• Time in Patent Office: 610 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/177 Smart card
• CPC Class Codes: G06F 2212/657 Virtual address space management

Abstract

A memory device comprises a first plurality of addressable memory locations associated with a first data storage window and a second plurality of addressable memory locations associated with a second data storage window. The memory device includes a controller that receives requests from a host device to identify the first data storage window and the second data storage window. The controller receives requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window. The controller receives memory commands from the host device that indicate the first window index value and at least one address. The controller accesses, based at least on the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.

Claims

1. A memory device comprising:

a first plurality of addressable memory locations, each of the first plurality of addressable memory locations having at least one memory cell, the first plurality of addressable memory locations collectively associated with a first data storage window;

a second plurality of addressable memory locations, each of the second plurality of addressable memory locations having at least one memory cell, the second plurality of addressable memory locations collectively associated with a second data storage window,

wherein the first data storage window and the second data storage window form a continuous memory address space; and

a memory device controller, coupled to the first plurality of addressable memory locations and to the second plurality of addressable memory locations, the memory device controller operable to;

receive one or more requests from a host device to identify the first data storage window and to identify the second data storage window;

receive one or more requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window;

receive one or more memory commands from the host device,

wherein the one or more memory commands indicate at least the first window index value and at least one address; and

access, based at least on the one or more memory commands indicating the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.

2. The memory device of claim 1, further comprising a first non-volatile memory entity physically separate from a second non-volatile memory entity, wherein the first data storage window is associated with the first non-volatile memory entity and the second data storage window is associated with the second non-volatile memory entity.

3. The memory device of claim 1, wherein the one or more requests to identify the first data storage window and to identify the second data storage window include a command to read a unique identifier from each of the data storage windows,

wherein the one or more requests from the host device to assign a window index value to each of the data storage windows includes a command for setting a relative memory device address, and

wherein the one or more requests to identify each of the data storage windows and the one or more requests to assign a window index value to each of the data storage windows are received in a repeating and alternating sequence until all data storage windows are identified and assigned window index values.

4. The memory device of claim 1, wherein the memory device controller is further operable to:

receive one or more commands for specifying a number of data storage windows; and

receive one or more commands for specifying a size of each data storage window.

5. The memory device of claim 1, wherein the continuous memory address space includes at least one of a continuous logical memory address space or a continuous physical memory address space.

6. The memory device of claim 1, wherein the host device provides window index values to respective data storage windows.

7. The memory device of claim 1, wherein the memory device controller is further operable to assign the first window index value and the second window index value, respectively, to the first data storage window and the second data storage window.

8. The memory device of claim 1, further comprising a third plurality of addressable memory locations, wherein the memory device controller is further operable to:

store the first window index value and the second window index value in the third plurality of addressable memory locations, and

provide the first window index value and the second window index value to the host device.

9. The memory device of claim 1, wherein at least one of the one or more memory commands from the host device is a memory device select/deselect command that indicates the first window index value and the second window index value.

10. A method of operating a memory device, the method comprising:

receiving one or more requests from a host device to identify a first data storage window and to identify a second data storage window, the first data storage window associated with a first plurality of addressable memory locations of the memory device, each of the first plurality of addressable memory locations having at least one memory cell, the second data storage window associated with a second plurality of addressable memory locations of the memory device, each of the second plurality of addressable memory locations having at least one memory cell, wherein the first data storage window and the second data storage window form a continuous memory address space;

receiving one or more requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window;

receiving one or more memory commands from the host device, wherein the one or more memory commands indicate at least the first window index value and at least one address; and

accessing, based at least on the one or more memory commands indicating the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.

11. The method of claim 10, further comprising:

associating the first data storage window with a first non-volatile memory entity; and

associating the second data storage window with a second non-volatile memory entity that is physically separate from the first non-volatile memory entity.

12. The method of claim 10, wherein the one or more requests to identify the first data storage window and to identify the second data storage window include a command to read a unique identifier from respective data storage windows, and

wherein the one or more requests from the host device to assign a window index value to each of the data storage windows includes a command for setting a relative memory device address.

13. The method of claim 10, further comprising receiving the one or more requests to identify respective data storage windows and the one or more requests to assign a window index value to the respective data storage windows in an alternating sequence, the alternating sequence repeated until the data storage windows are identified and assigned window index values.

14. The method of claim 10, further comprising:

receiving one or more commands for specifying a number of data storage windows, and

receiving one or more commands for specifying a size of each data storage window.

15. The method of claim 10, wherein the continuous memory address space includes at least one of a continuous logical memory address space or a continuous physical memory address space.

16. The method of claim 10, further comprising assigning the first window index value and the second window index value, respectively, to the first data storage window and the second data storage window.

17. A host device comprising:

a memory interface configured to be coupled to a memory device, the memory device comprising;

a first plurality of addressable memory locations, each of the first plurality of addressable memory locations having at least one memory cell, the first plurality of addressable memory locations collectively associated with a first data storage window;

a second plurality of addressable memory locations, each of the second plurality of addressable memory locations having at least one memory cell, the second plurality of addressable memory locations collectively associated with a second data storage window,

wherein the first data storage window and the second data storage window form a continuous memory address space; and

a host controller operable to;

send one or more requests to the memory device to identify the first data storage window and to identify the second data storage window;

send one or more requests to the memory device to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window;

send one or more memory commands to the memory device, wherein the one or more memory commands indicate at least the first window index value and at least one address; and

receive, based at least on the one or more memory commands indicating the first window index value, data stored at a location associated with the at least one address within the first plurality of addressable memory locations.

18. The host device of claim 17, wherein the one or more requests to identify the first data storage window and to identify the second data storage window include a command to read a unique identifier from each of the data storage windows,

wherein the one or more requests to assign a window index value to each of the data storage windows includes a command for setting a relative memory device address, and

wherein the one or more requests to identify each of the data storage windows and the one or more requests to assign a window index value to each of the data storage windows are sent in a repeating and alternating sequence until all data storage windows are identified and assigned window index values.

19. The host device of claim 17, wherein the host controller is further operable to:

send one or more commands for specifying a number of data storage windows, and

send one or more commands for specifying a size of each data storage window.

20. The host device of claim 17, wherein the host controller is further operable to provide window index values to respective data storage windows.