Methods, devices and systems for solid state drive control

• US 10,055,345 B2
• Filed: 11/07/2016
• Issued: 08/21/2018
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Tomlin, Andrew J., Mullendore, Rodney N., Jones, Justin
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Grullon, Francisco A
• Application Number:
  US15/345,100
• Publication Number:
  US 20170075807A1
• Time in Patent Office: 652 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A solid state drive controller includes a processor configured to couple to a plurality of non-volatile memory devices. The plurality of non-volatile memory devices are configured to store a plurality of system journals and a plurality of physical pages. The solid state drive controller also includes a volatile memory configured to store a logical-to-physical address translation map configured to enable the solid state drive controller to determine a physical location of at least one logical page. The processor is configured to maintain the plurality of system journals in the plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of the plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages.

Claims

1. A solid state drive controller, comprising:

a processor configured to couple to a plurality of non-volatile memory devices, wherein the plurality of non-volatile memory devices are configured to store a plurality of system journals and a plurality of physical pages; and

a volatile memory configured to store a logical-to-physical address translation map configured to enable the solid state drive controller to determine a physical location of at least one logical page,

wherein the processor is configured to;

maintain the plurality of system journals in the plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of the plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages;

determine that the logical-to-physical address translation map needs to be rebuilt;

read information from the plurality of system journals when the logical-to-physical address translation map needs to be rebuilt; and

rebuild the logical-to-physical address translation map using the information read from the plurality of system journals.

2. The solid state drive controller of claim 1, wherein the portion of the address of the first physical page includes a number of the most significant bits of the address of the first physical page.

3. The solid state drive controller of claim 2, wherein each system journal includes an entry that points to a starting address of a logical page of the at least one logical pages.

4. The solid state drive controller of claim 3, wherein the entry includes a number of least significant bits of an address of a physical page of the predetermined range of the plurality of physical pages that contains the starting address of the logical page of the at least one logical pages.

5. The solid state drive controller of claim 4, wherein a full physical page address is obtained by concatenating the number of the most significant bits with the number of the least significant bits.

6. The solid state drive controller of claim 4, wherein the entry includes an offset of the logical page of the at least one logical pages within the physical page of the predetermined range of the plurality of physical pages.

7. The solid state drive controller of claim 1, wherein a header of each system journal includes the identification number.

8. The solid state drive controller of claim 1, wherein determining that the logical-to-physical address translation map needs to be rebuilt includes determining that the logical-to-physical address translation map needs to be partially rebuilt.

9. The solid state drive controller of claim 1, wherein determining that the logical-to-physical address translation map needs to be rebuilt includes determining that the logical-to-physical address translation map needs to be entirely rebuilt.

10. The solid state drive controller of claim 1, wherein a variable number of the at least one logical page is stored in the predetermined range of physical pages.

11. A method for controlling a solid state drive, the method comprising:

maintaining a plurality of system journals in a plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of a plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages;

determining that a logical-to-physical address translation map needs to be rebuilt, wherein the logical-to-physical address translation map is stored in a volatile memory;

reading information from the plurality of system journals when the logical-to-physical address translation map needs to be rebuilt; and

rebuilding the logical-to-physical address translation map using the information read from the plurality of system journals.

12. The method of claim 11, wherein the portion of the address of the first physical page includes a number of the most significant bits of the address of the first physical page.

13. The method of claim 12, wherein each system journal includes an entry that points to a starting address of a logical page of the at least one logical pages.

14. The method of claim 13, wherein the entry includes a number of least significant bits of an address of a physical page of the predetermined range of the plurality of physical pages that contains the starting address of the logical page of the at least one logical pages.

15. The method of claim 14, wherein a full physical page address is obtained by concatenating the number of the most significant bits with the number of the least significant bits.

16. A data storage device, comprising:

a plurality of non-volatile memory devices configured to store a plurality of system journals and a plurality of physical pages; and

a solid state controller, wherein the solid state controller includes;

a processor coupled to the plurality of non-volatile memory devices; and

a volatile memory configured to store a logical-to-physical address translation map configured to enable the solid state controller to determine a physical location of at least one logical page, wherein the processor is configured to;

maintain the plurality of system journals in the plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of the plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages;

determine that the logical-to-physical address translation map needs to be rebuilt;

read information from the plurality of system journals when the logical-to-physical address translation map needs to be rebuilt; and

rebuild the logical-to-physical address translation map using the information read from the plurality of system journals.

17. The data storage device of claim 16, wherein the portion of the address of the first physical page includes a number of the most significant bits of the address of the first physical page.

18. The data storage device of claim 17, wherein each system journal includes an entry that points to a starting address of a logical page of the at least one logical pages.

19. The data storage device of claim 18, wherein the entry includes a number of least significant bits of an address of a physical page of the predetermined range of the plurality of physical pages that contains the starting address of the logical page of the at least one logical pages.

20. The data storage device of claim 19, wherein a full physical page address is obtained by concatenating the number of the most significant bits with the number of the least significant bits.

21. A solid state drive controller, comprising:

means for maintaining a plurality of system journals in a plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of a plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages;

means for determining that a logical-to-physical address translation map needs to be rebuilt, wherein the logical-to-physical address translation map is stored in a volatile memory;

means for reading information from the plurality of system journals when the logical-to-physical address translation map needs to be rebuilt; and

means for rebuilding the logical-to-physical address translation map using the information read from the plurality of system journals.

22. The solid state drive controller of claim 21, wherein the portion of the address of the first physical page includes a number of the most significant bits of the address of the first physical page.

23. The solid state drive controller of claim 22, wherein each system journal includes an entry that points to a starting address of a logical page of the at least one logical pages.

24. The solid state drive controller of claim 23, wherein the entry includes a number of least significant bits of an address of a physical page of the predetermined range of the plurality of physical pages that contains the starting address of the logical page of the at least one logical pages.

25. The solid state drive controller of claim 24, wherein a full physical page address is obtained by concatenating the number of the most significant bits with the number of the least significant bits.