Apparatus, method and system that stores bios in non-volatile random access memory

• US 10,055,353 B2
• Filed: 08/29/2016
• Issued: 08/21/2018
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nachimuthu, Murugasamy K., Kumar, Mohan
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Westbrook, Michael L
• Application Number:
  US15/250,832
• Publication Number:
  US 20170052896A1
• Time in Patent Office: 722 Days
• Field of Search: None
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS.

Claims

1. An apparatus comprising:

a processor comprising;

a processing core;

a first interface to couple the processor to a non-volatile memory (NVM), the NVM to store a compressed Basic Input and Output System (BIOS) image;

a cache to support execution of a boot process; and

a second interface to couple the processing core to a non-volatile random access memory, the processing core to execute program code directly out of the non-volatile random access memory, the non-volatile random access memory having a larger capacity and a lower latency than the NVM, the non-volatile random access memory to store an uncompressed BIOS image, wherein the uncompressed BIOS image is to be produced by the processor from the compressed BIOS image during a boot process, wherein the cache is permitted to write back to the non-volatile random access memory during execution of the uncompressed BIOS image from the cache.

2. The apparatus of claim 1, wherein the non-volatile random access memory comprises any of:

a phase change memory (PCM);

chalcogenide glass;

resistive memory;

ferro-electric memory;

magnetic memory;

spin-transfer torque memory;

spin-tunneling memory;

dielectric memory.

3. The apparatus of claim 1, wherein the first interface is part of an I/O subsystem and the second interface is not part of an I/O subsystem.

4. The apparatus of claim 1, wherein the second interface implements a same protocol as inter-processor links.

5. The apparatus of claim 1, wherein the NVM is a flash memory.

6. The apparatus of claim 1, wherein the non-volatile random access memory comprises a writable area to which debug or error or progress status messages generated during the boot process are written.

7. The apparatus of claim 1, wherein, the non-volatile random access memory is part of a system memory.

8. A non transitory machine readable storage medium containing firmware program code that when processed by a computing system causes a method to be performed, the method comprising:

executing a boot-up process for the computing system, the computing system comprising a non-volatile memory and a non-volatile random access memory, the non-volatile random access memory having a larger capacity and a lower latency than the non-volatile memory, the executing comprising;

a) during the boot-up process, executing from a cache placed in a non write back mode, reading a compressed portion of the boot-up process'"'"'s program code stored in the non-volatile memory;

b) causing a decompression process to be performed on the compressed portion to form an uncompressed portion of the boot-up process'"'"'s program code and storing the uncompressed portion in the non-volatile random access memory; and

,

c) changing the cache to a write back mode and continuing the boot up process by executing the uncompressed portion from the cache.

9. The machine readable storage medium of claim 8, wherein the non-volatile random access memory comprises any of:

a phase change memory (PCM);

chalcogenide glass;

resistive memory;

ferro-electric memory;

magnetic memory;

spin-transfer torque memory;

spin-tunneling memory;

dielectric memory.

10. The machine readable storage medium of claim 8 wherein the reading is performed over an I/O subsystem interface and the storing is performed over a non-I/O subsystem interface.

11. The machine readable storage medium of claim 8 wherein the storing occurs after inter-processor links have been initialized.

12. The machine readable storage medium of claim 8 wherein the non-volatile memory is a flash memory.

13. The machine readable storage medium of claim 8 wherein the non-volatile random access memory comprises a writable area to which debug or error or progress status messages generated during the boot up process are written.

14. A computing system, comprising:

one or more processors;

an I/O subsystem coupled to a non-volatile memory (NVM), the NVM to store a compressed Basic Input and Output System (BIOS) image;

a cache to support execution of a boot process; and

,

an interface coupled between the one or more processors and a non-volatile random access memory, at least one of the one or more processors to execute program code directly out of the non-volatile random access memory, the non-volatile random access memory having a larger capacity and a lower latency than the NVM, the non-volatile random access memory to store an uncompressed BIOS image, wherein the uncompressed BIOS image is to be produced by the computing system from the compressed BIOS image during a boot process, wherein the cache is permitted to write back to the non-volatile random access memory during execution of the uncompressed BIOS image from the cache.

15. The computing system of claim 14 wherein the non-volatile random access memory comprises any of:

a phase change memory (PCM);

chalcogenide glass;

resistive memory;

ferro-electric memory;

magnetic memory;

spin-transfer torque memory;

spin-tunneling memory;

dielectric memory.

16. The computing system of claim 14 wherein the interface implements a same protocol as inter-processor links within the computing system.

17. The computing system of claim 14, wherein the NVM is a flash memory.

18. The computing system of claim 14 wherein the non-volatile random access memory comprises a writable area to which debug or error or progress status messages generated during the boot process are written.

19. The computing system of claim 14 wherein the uncompressed BIOS image is stored in the non-volatile random access memory after the non-volatile random access memory has been initialized by the boot up process.

20. The computing system of claim 19 wherein the non-volatile random access memory has been initialized by the boot up process after the interface has been initialized by the boot up process.