Orthogonal differential vector signaling codes with embedded clock
First Claim
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1. An apparatus comprising:
- a first subchannel encoder configured to receive a first input signal and to generate elements of a first weighted subchannel vector;
a second subchannel encoder configured to receive a second input signal, and to generate elements of a second weighted subchannel vector, wherein the second weighted subchannel vector is mutually orthogonal to the first weighted subchannel vector and wherein the second input signal is asynchronous with respect to the first input signal;
an asynchronous codeword generator connected to the first and second subchannel encoders, the asynchronous codeword generator configured to receive the first and second subchannel vectors and to responsively generate elements of an asynchronous-transmit codeword by adding the first and second weighted subchannel vectors, wherein elements of the asynchronous-transmit codeword transition asynchronously in response to transitions of elements of the first or second weighted subchannel vector; and
a driver configured to transmit the elements of the asynchronous-transmit codeword as analog signals on a multi-wire bus.
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Abstract
Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
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Citations
20 Claims
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1. An apparatus comprising:
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a first subchannel encoder configured to receive a first input signal and to generate elements of a first weighted subchannel vector; a second subchannel encoder configured to receive a second input signal, and to generate elements of a second weighted subchannel vector, wherein the second weighted subchannel vector is mutually orthogonal to the first weighted subchannel vector and wherein the second input signal is asynchronous with respect to the first input signal; an asynchronous codeword generator connected to the first and second subchannel encoders, the asynchronous codeword generator configured to receive the first and second subchannel vectors and to responsively generate elements of an asynchronous-transmit codeword by adding the first and second weighted subchannel vectors, wherein elements of the asynchronous-transmit codeword transition asynchronously in response to transitions of elements of the first or second weighted subchannel vector; and a driver configured to transmit the elements of the asynchronous-transmit codeword as analog signals on a multi-wire bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving, at a first subchannel encoder, a first input signal and responsively generating elements of a first weighted subchannel vector; receiving, at a second subchannel encoder, a second input signal and responsively generating elements of a second weighted subchannel vector, wherein the second weighted subchannel vector is mutually orthogonal to the first weighted subchannel vector and wherein the second input signal is asynchronous with respect to the first input signal; generating, using an asynchronous codeword generator, elements of an asynchronous-transmit codeword by adding the first and second weighted subchannel vectors, wherein elements of the asynchronous-transmit codeword transition asynchronously in response to transitions of elements of the first or second weighted subchannel vector; and transmitting the elements of the asynchronous-transmit codeword as multi-level analog signals on a multi-wire bus. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification