Matrix circuits

• US 10,055,383 B1
• Filed: 04/28/2017
• Issued: 08/21/2018
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Shafiee Ardestani, Ali, Muralimanohar, Naveen
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US15/581,110
• Time in Patent Office: 480 Days
• Field of Search: 708520, 708607
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

Claims

1. A circuit comprising:

a memory array including;

a plurality of memory cells to store a matrix; and

a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix;

a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values;

a summing unit coupled to the multiplier to sum the third set of values to produce a sum; and

a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

2. The circuit of claim 1, wherein each of the plurality of memory cells includes:

a capacitor;

an access transistor coupled to the capacitor to program the capacitor; and

a pass transistor having a gate coupled to the capacitor to read a value of the matrix that is stored in the capacitor, wherein the value is provided to a corresponding data line of the plurality of data lines.

3. The circuit of claim 2, wherein the access transistor of each of the plurality of memory cells is coupled between the capacitor and a column write line to program the memory array a row at a time.

4. The circuit of claim 3, wherein the pass transistor of each of the plurality of memory cells is coupled to a row read line to read the memory array a column at a time.

5. The circuit of claim 1, wherein each of the plurality of memory cells includes:

a resistive memory device;

an access transistor coupled to the resistive memory device to program the resistive memory device; and

a pass transistor coupled to the resistive memory device to read a value of the matrix that is encoded in the resistive memory device, wherein the value is provided to a corresponding data line of the plurality of data lines.

6. The circuit of claim 1, wherein the memory array, the multiplier, the summing unit, and the shifting unit are to multiply the matrix by a vector that includes the second set of values.

7. The circuit of claim 1, wherein the matrix includes a plurality of multi-bit values, and wherein the first set of values of the matrix have a common place value.

8. The circuit of claim 1, wherein the shifting unit is to shift the sum based on a place value of the first set of values or a place value of the second set of values.

9. A circuit comprising:

a memory array to store a matrix that includes a plurality of multi-bit values, wherein the plurality of multi-bit values includes a plurality of matrix sets, and wherein each set of the plurality of matrix sets contains values having a common place value; and

a matrix processing unit coupled to the memory array and including logic to, for each set of the plurality of matrix sets;

receive the respective set;

multiply the respective set by a vector set;

sum each element of the product of the respective set and the vector set to produce a total;

shift the total; and

add the shifted total to a running total.

10. The circuit of claim 9, wherein the memory array stores the matrix in a plurality of memory cells, and wherein each memory cell includes:

a capacitor;

an access transistor coupled to the capacitor to program the capacitor; and

a pass transistor having a gate coupled to the capacitor to read a value of the matrix that is stored in the capacitor.

11. The circuit of claim 10, wherein the access transistor of each of the plurality of memory cells is coupled between the capacitor and a column line to program the memory array a row at a time.

12. The circuit of claim 11, wherein the pass transistor of each of the plurality of memory cells is coupled to a row line to read the memory array a column at a time.

13. The circuit of claim 9, wherein the memory array stores the matrix in a plurality of memory cells, and wherein each of the plurality of memory cells includes:

a resistive memory device;

an access transistor coupled to the resistive memory device to program the resistive memory device; and

a pass transistor coupled to the resistive memory device to read a value of the matrix that is encoded in the resistive memory device.

14. The circuit of claim 9, wherein the vector multiplication unit is to shift the total based on a place value of the respective set of the plurality of matrix sets or a place value of the vector set.

15. A method comprising:

reading a first set of values of a matrix from a memory array;

multiplying the first set of values of the matrix by a second set of values of a vector to provide a third set of values;

summing the third set of values to produce a sum;

shifting the sum based on a place value of the first set of values or a place value of the second set of values; and

adding the shifted sum to a running total.

16. The method of claim 15 comprising writing the matrix to the memory array a row at a time.

17. The method of claim 16, wherein the reading of the first set of values reads from the memory array a column at a time.

18. The method of claim 15, wherein the matrix includes a plurality of multi-bit values, and wherein the first set of values of the matrix have a common place value.

19. The method of claim 15, wherein the memory array includes a plurality of capacitors that store the matrix, and wherein the reading of the first set of values retains the first set of values within the plurality of capacitors.

20. The method of claim 15, wherein the memory array includes a plurality of resistive memory devices that store the matrix.