Methods, systems, and computer program product for implementing engineering change orders with figure groups and virtual hierarchies

• US 10,055,528 B1
• Filed: 09/30/2016
• Issued: 08/21/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ginetti, Arnold
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US15/282,739
• Time in Patent Office: 690 Days
• Field of Search: 716119
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

Claims

1. A computer implemented method for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies, comprising:

performing a process at least by executing a sequence of instructions with at least an ECO module functioning in tandem with a micro-processor of a computing system, the process comprising;

identifying a schematic design and a layout comprising at least one virtual hierarchy of an electronic design;

implementing an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout;

checking the figure group based in part or in whole upon one or more criteria; and

updating one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

2. The computer implemented method of claim 1, the process further comprising:

maintaining a one-to-one mapping between figure groups in the layout and schematic instances in the schematic design.

3. The computer implemented method of claim 2, further comprising:

identifying one or more schematic instances that do not correspond to figure groups in the layout from at least one data structure of the one or more data structures; and

generating one or more figure groups for the one or more schematic instances that have been identified not to correspond to the figure groups.

4. The computer implemented method of claim 3, further comprising:

determining one or more virtual hierarchies at which the one or more figure groups are respectively located; and

updating the one or more data structures for the one or more figure groups and for the one or more virtual hierarchies.

5. The computer implemented method of claim 1, further comprising:

maintaining synchronous clones for a plurality of figure groups at one or more virtual hierarchies.

6. The computer implemented method of claim 5, further comprising:

identifying the plurality of figure groups;

identifying the one or more virtual hierarchies at which the plurality of figure groups are respectively located; and

determining whether the plurality of figure groups have a same topology.

7. The computer implemented method of claim 6, further comprising:

identifying one or more common hierarchical parameters shared by the plurality of figure groups; and

determining whether the plurality of figure groups have same hierarchical parameter values for the one or more common hierarchical parameters.

8. The computer implemented method of claim 7, further comprising:

creating a plurality of synchronous clones for the plurality of figure groups; and

updating the one or more data structures with information about the plurality of synchronous clones for the plurality of figure groups.

9. The computer implemented method of claim 1, checking the figure group based in part or in whole upon one or more criteria comprising:

identifying a schematic instance from the schematic design based in part or in whole upon the at least one layout circuit component and binding information between the schematic design and the layout;

identifying a set of layout circuit component designs and layout connectivity from the figure group; and

identifying a set of schematic circuit component designs and schematic connectivity from the schematic instance.

10. The computer implemented method of claim 9, checking the figure group based in part or in whole upon one or more criteria comprising:

determining whether the set of layout circuit component designs in the figure group correspond to the set of schematic circuit component designs in the schematic instance to generate a first determination result; and

updating the figure group or the schematic instance when one or more discrepancies are identified in the first determination result.

11. The computer implemented method of claim 9, checking the figure group based in part or in whole upon one or more criteria comprising:

determining whether the and layout connectivity for or in the figure group is identical to the schematic connectivity for or in the schematic instance to generate a second determination result; and

updating the figure group or the schematic instance when one or more discrepancies are identified in the second determination result.

12. The computer implemented method of claim 1, further comprising:

determining whether the layout includes a physical hierarchical portion corresponding a physical hierarchical structure having multiple physical hierarchies;

determining whether the ECO changes the physical hierarchical structure;

determining whether the ECO changes a virtual hierarchical structure having at least the at least one virtual hierarchy; and

updating the virtual hierarchical structure to be in sync with a schematic hierarchical structure of the schematic design.

13. A system for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies, comprising:

non-transitory computer accessible storage medium storing thereupon program code;

at least one processor executing the program code to identify a schematic design and a layout comprising at least one virtual hierarchy of an electronic design;

one or more modules that are stored at least partially in memory of one or more computing systems, include or function in conjunction with at least one hardware processor of the one or more computing systems, and are configured to execute the program code to implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout;

the at least one processor further executing the program code to check the figure group based in part or in whole upon one or more criteria; and

the at least one processor further executing the program code to update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

14. The system for claim 13, the at least one processor further executing the program code to maintain a one-to-one mapping between figure groups in the layout and schematic instances in the schematic design.

15. The system for claim 13, the at least one processor further executing the program code to identify one or more schematic instances that do not correspond to figure groups in the layout from at least one data structure of the one or more data structures, to generate one or more figure groups for the one or more schematic instances that have been identified not to correspond to the figure groups, to determine one or more virtual hierarchies at which the one or more figure groups are respectively located, and to update the one or more data structures for the one or more figure groups and for the one or more virtual hierarchies.

16. The system for claim 13, the at least one processor further executing the program code at least to maintain synchronous clones for a plurality of figure groups at one or more virtual hierarchies at least by identifying the plurality of figure groups, identifying the one or more virtual hierarchies at which the plurality of figure groups are respectively located, determining whether the plurality of figure groups have a same topology, identifying one or more common hierarchical parameters shared by the plurality of figure groups, determining whether the plurality of figure groups have same hierarchical parameter values for the one or more common hierarchical parameters, creating a plurality of synchronous clones for the plurality of figure groups, and updating the one or more data structures with information about the plurality of synchronous clones for the plurality of figure groups.

17. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies, the set of acts comprising:

performing a process at least by executing a sequence of instructions with at least an ECO module functioning in tandem with a micro-processor of a computing system, the process comprising;

identifying a schematic design and a layout comprising at least one virtual hierarchy of an electronic design;

implementing an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout;

checking the figure group based in part or in whole upon one or more criteria; and

updating one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

18. The article of manufacture of claim 17, the set of acts further comprising:

maintaining a one-to-one mapping between figure groups in the layout and schematic instances in the schematic design, maintaining the one-to-one mapping comprising;

identifying one or more schematic instances that do not correspond to figure groups in the layout from at least one data structure of the one or more data structures;

generating one or more figure groups for the one or more schematic instances that have been identified not to correspond to the figure groups;

determining one or more virtual hierarchies at which the one or more figure groups are respectively located; and

updating the one or more data structures for the one or more figure groups and for the one or more virtual hierarchies.

19. The article of manufacture of claim 17, the set of acts further comprising:

maintaining synchronous clones for a plurality of figure groups at one or more virtual hierarchies, maintaining the synchronous clones comprising;

identifying the plurality of figure groups;

identifying the one or more virtual hierarchies at which the plurality of figure groups are respectively located;

determining whether the plurality of figure groups have a same topology;

identifying one or more common hierarchical parameters shared by the plurality of figure groups;

determining whether the plurality of figure groups have same hierarchical parameter values for the one or more common hierarchical parameters;

creating a plurality of synchronous clones for the plurality of figure groups; and

updating the one or more data structures with information about the plurality of synchronous clones for the plurality of figure groups.

20. The article of manufacture of claim 17, the set of acts further comprising:

identifying a schematic instance from the schematic design based in part or in whole upon the at least one layout circuit component and binding information between the schematic design and the layout;

identifying a set of layout circuit component designs and layout connectivity from the figure group;

identifying a set of schematic circuit component designs and schematic connectivity from the schematic instance;

determining whether the set of layout circuit component designs in the figure group correspond to the set of schematic circuit component designs in the schematic instance to generate a first determination result;

determining whether the and layout connectivity for or in the figure group is identical to the schematic connectivity for or in the schematic instance to generate a second determination result; and

updating the figure group or the schematic instance when one or more discrepancies are identified in the first determination result or in the second determination result.