Methods, systems, and computer program product for implementing a floorplan with virtual hierarchies and figure groups for an electronic design

• US 10,055,529 B1
• Filed: 09/30/2016
• Issued: 08/21/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ginetti, Arnold
• Primary Examiner(s): Lin, Sun
• Application Number:
  US15/283,089
• Time in Patent Office: 690 Days
• Field of Search: 716100, 716118, 716119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At least one layout circuit component design of the plurality of layout circuit component designs can then be reinstalled into the modified figure group to fulfill the request for modification of the figure group.

Claims

1. A computer-implemented method for implementing a floorplan with virtual hierarchies and figure groups for an electronic design, the computer-implemented method comprising:

executing, at a floorplanning module coupled to a micro-processor of a computing system, a sequence of instructions to perform a process, the process comprising;

identifying a plurality of layout circuit component designs in a layout of an electronic design;

identifying or creating a figure group for the plurality of layout circuit component designs in the layout;

modifying, at the floorplanning module, the layout into a modified layout in response to a request for a modification of the figure group at least by applying one or more modifications of the layout to the figure group; and

reinstalling at least one layout circuit component design of the plurality of layout circuit component designs in the modified figure group.

2. The computer-implemented method of claim 1, the process further comprising:

materializing the modified figure group into a physical cell or a physical block; and

updating a layout database with information about the physical cell or the physical block.

3. The computer-implemented method of claim 2, wherein the process further comprises:

identifying a virtual hierarchy at which the modified figure group is located;

determining whether the virtual hierarchy has been materialized; and

materializing the virtual hierarchy into a physical hierarchy when the virtual hierarchy is determined not to have been materialized.

4. The computer-implemented method of claim 3, wherein the process further comprises:

identifying a physical hierarchical structure comprising one or more physical hierarchies for the layout;

updating the physical hierarchical structure to add the physical hierarchy to the physical hierarchical structure when the virtual hierarchy is materialized in response to a determination that the virtual hierarchy has not been materialized; and

updating a layout database with information about the physical hierarchy.

5. The computer-implemented method of claim 1, wherein the process further comprises:

identifying a boundary object of the figure group;

receiving the request for the modification; and

modifying the figure group into the modified figure group at least by altering the boundary object into a modified boundary object having a size or a shape different from that of the boundary object.

6. The computer-implemented method of claim 5, wherein the process further comprises:

removing the plurality of layout circuit component designs from the figure group; and

reinserting the plurality of layout circuit component designs into the modified boundary object of the modified figure group.

7. The computer-implemented method of claim 6, wherein the process further comprises:

identifying one or more design rules; and

improving an arrangement of the plurality of layout circuit component designs at least by invoking a placement engine to place the plurality of circuit component designs based in part or in whole upon the one or more design rules.

8. The computer-implemented method of claim 5, wherein the process further comprises:

removing one or more layout circuit component designs but not the plurality of layout circuit component designs from the figure group; and

reinserting the one or more layout circuit component designs into the modified boundary object of the modified figure group.

9. The computer-implemented method of claim 8, wherein the process further comprises:

adjusting one or more other layout circuit component designs in the modified figure group in response to the act of reinserting the one or more layout circuit component designs into the modified boundary object of the modified figure group.

10. The computer-implemented method of claim 5, wherein the process further comprises:

identifying one or more design rules; and

improving an arrangement of the plurality of layout circuit component designs at least by invoking a placement engine to place the plurality of circuit component designs based in part or in whole upon the one or more design rules.

11. The computer-implemented method of claim 5, wherein the process further comprises:

determining whether the plurality of layout circuit component designs fit within the modified boundary object;

recommending a new modified boundary object for the modified figure group, wherein the plurality of layout circuit component designs fit within the new modified boundary object; and

overlaying the new modified boundary object in a user interface with the modified boundary object for the modified figure group.

12. The computer-implemented method of claim 5, wherein the process further comprises:

determining whether the plurality of layout circuit component designs fit within the modified boundary object; and

forcing the plurality of layout circuit component designs within the modified boundary object when the plurality of layout circuit component designs are determined not to fit within the modified boundary object.

13. The computer-implemented method of claim 1, wherein the process further comprises:

determining whether a group of synchronous clones have been created for the figure group;

modifying a master block for the group of synchronous clones according to the request for the modification; and

populating the modification to one or more other synchronous clones in the group of synchronous clones.

14. The computer-implemented method of claim 1, wherein the process further comprises:

identifying one or more design rules;

improving an arrangement of the plurality of layout circuit component designs at least by invoking a placement engine to place the plurality of circuit component designs to generate a placed figure group based in part or in whole upon the one or more design rules;

materializing the placed figure group into a physical cell or a physical block; and

updating a layout database with information about the physical cell or the physical block.

15. A system for implementing clones for an electronic design, the system comprising:

non-transitory computer accessible storage medium storing thereupon program code;

a physical implementation module that is stored at least partially in memory of one or more computing systems, include or function in conjunction with at least one micro-processor of the one or more computing systems, and are configured to execute the program code to identify a plurality of layout circuit component designs in a layout of an electronic design;

the physical implementation module further executing the program code to identify or create a figure group for the plurality of layout circuit component designs in the layout;

the physical implementation module further executing the program code to modify the figure group into a modified figure group in response to a request for a modification of the figure group at least by applying one or more modifications of the layout to the figure group; and

the physical implementation module further executing the program code to reinstall at least one layout circuit component design of the plurality of layout circuit component designs in the modified figure group.

16. The system for claim 15, the physical implementation module further executing the program code to:

materialize the modified figure group into a physical cell or a physical block;

update a layout database with information about the physical cell or the physical block;

identify a virtual hierarchy at which the modified figure group is located; and

determine whether the virtual hierarchy has been materialized.

17. The system for claim 16, the physical implementation module further executing the program code to:

materialize the virtual hierarchy into a physical hierarchy when the virtual hierarchy is determined not to have been materialized;

identify a physical hierarchical structure comprising one or more physical hierarchies for the layout;

update the physical hierarchical structure to add the physical hierarchy to the physical hierarchical structure when the virtual hierarchy is materialized in response to a determination that the virtual hierarchy has not been materialized; and

update a layout database with information about the physical hierarchy.

18. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing a floorplan with virtual hierarchies and figure groups for an electronic design, the set of acts comprising:

executing, at a floorplanning module coupled to a micro-processor of a computing system, a sequence of instructions to perform a process, the process comprising;

identifying a plurality of layout circuit component designs in a layout of an electronic design;

identifying or creating a figure group for the plurality of layout circuit component designs in the layout;

modifying, at the floorplanning module, the figure group into a modified figure group in response to a request for a modification of the figure group at least by applying one or more modifications of the layout to the figure group; and

reinstalling at least one layout circuit component design of the plurality of layout circuit component designs in the modified figure group.

19. The article of manufacture of claim 18, the set of acts further comprising:

identifying a boundary object of the figure group;

receiving the request for the modification;

modifying the figure group into the modified figure group at least by altering the boundary object into a modified boundary object having a size or a shape different from that of the boundary object;

removing the plurality of layout circuit component designs from the figure group; and

reinserting the plurality of layout circuit component designs into the modified boundary object of the modified figure group.

20. The article of manufacture of claim 19, the set of acts further comprising:

determining whether the plurality of layout circuit component designs fit within the modified boundary object;

recommending a new modified boundary object for the modified figure group, wherein the plurality of layout circuit component designs fit within the new modified boundary object; and

overlaying the new modified boundary object in a user interface with the modified boundary object for the modified figure group or forcing the plurality of layout circuit component designs within the modified boundary object when the plurality of layout circuit component designs are determined not to fit within the modified boundary object.