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Method, system and program product for identifying anomalies in integrated circuit design layouts

  • US 10,055,535 B2
  • Filed: 09/27/2016
  • Issued: 08/21/2018
  • Est. Priority Date: 09/27/2016
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • providing a data representation of at least one integrated circuit design layout and one or more input parameters to a memory in communication with a processor;

    deconstructing, by the processor according to instructions stored in the memory, the data representation into a plurality of unit-level geometric constructs;

    identifying, by the processor according to instructions stored in the memory, anomalies in the plurality of unit-level geometric constructs, wherein the identifying is based on only the plurality of unit-level geometric constructs;

    storing, by the processor according to instructions stored in the memory, anomaly data in a database, wherein the providing, the deconstructing, the identifying and the storing are performed prior to semiconductor manufacturing; and

    using the anomaly data to perform semiconductor manufacturing, the using improving semiconductor manufacturing yield as compared to not using the anomaly data.

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