Group information storing and recognizing apparatus

• US 10,055,683 B2
• Filed: 08/11/2014
• Issued: 08/21/2018
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamaguchi, Hitoshi
• Primary Examiner(s): Chaki, Kakali
• Assistant Examiner(s): Pellett, Daniel
• Application Number:
  US14/456,002
• Publication Number:
  US 20150100532A1
• Time in Patent Office: 1,471 Days
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.

Claims

1. An electronic apparatus comprising:

a neuron element including a first field-effect transistor that includes a semiconductor substrate including a first semiconductor layer where a channel is formed,

a first source region and a first drain region formed in a surface part of the first semiconductor layer,

a gate insulating film formed over the channel,

a floating gate electrode formed over the gate insulating film,

a first ferroelectric film formed over the floating gate electrode and accumulating electric charges according to the number of times of voltage application, and

a multi-input gate electrode including a plurality of gate electrodes arranged at intervals over the first ferroelectric film; and

a plurality of synapse circuits,

each synapse circuit that is configured to receive, from one of a plurality of image regions of an information input part, an input voltage of a high level signal or a low level signal that is lower than the high level signal,

each synapse circuit being electrically connected to one of the plurality of gate electrodes of the multi-input gate electrode of the neuron element,

each synapse circuit including

a second field-effect transistor that includes a second ferroelectric film in which charge from the high level signal accumulates and that turns ON after a predetermined amount of charge from the high level signal accumulates on the second ferroelectric film,

wherein after the second field-effect transistor is turned ON, an input of either the high level signal or the low level signal is transmitted directly to one of the plurality of gate electrodes of the multi-gate electrode to cause the synapse circuit to function as a signal through circuit, and

a NOT gate that is electrically connected in parallel to the second field-effect transistor, that is configured to convert the high level signal to an inverted low-level signal and the low level signal to an inverted high-level signal and that includes an input and an output, and

a third field-effect transistor that is electrically connected to the output of the NOT gate in series to receive the inverted low-level signal or the inverted high-level signal,

the third field-effect transistor that includes a third ferroelectric film in which charge from the inverted high-level signal accumulates, and that turns ON after a predetermined amount of charge from the inverted high-level signal output by the NOT gate accumulates on the third ferroelectric film,

wherein after the third field-effect transistor is turned ON, an input of either the inverted high-level signal or the inverted low-level signal from the NOT gate to the third field-effect transistor is transmitted directly to one of the plurality of gate electrodes of the multi-gate electrode, so that an input of either the high level signal or the low level signal to the NOT gate is transmitted inversely to one of the plurality of gate electrodes of the multi-gate electrode via the third field-effect transistor to cause the synapse circuit to function as a signal inverted circuit.

2. The electronic apparatus according to claim 1, wherein:

when all inputs from the plurality of image regions of the information input part to the respective synapse circuits are maintained unchanged after turning ON, all output signals of the plurality of synapse circuits to the respective gate electrodes of the multi-gate electrode each continue to be the high level signal regardless whether each of the synapse circuits functions as the signal through circuit or the signal inverted circuit, to cause the neuron element to be prone to turn ON; and

when any one of all inputs from the plurality of image regions to the respective synapse circuits is changed after turning ON, an output of a corresponding synapse circuit among the plurality of synapse circuits to a corresponding gate electrode among the plurality of gate electrodes of the multi-gate electrode becomes the low level signal regardless of whether each of the synapse circuits functions as the signal through circuit or the signal inverted circuit, to cause the neuron element to be less prone to turn ON.

3. The electronic apparatus according to claim 1, wherein:

the output of the NOT gate is connected to a common node shared by two terminals of the second field effect transistor.