Integrated circuit using topology configurations

• US 10,056,121 B2
• Filed: 03/06/2017
• Issued: 08/21/2018
• Est. Priority Date: 03/16/2015
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Arm Limited (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Khayatzadeh, Mahmood, Alioto, Massimo Bruno, Blaauw, David Theodore, Sylvester, Dennis Michael Chen, Bohra, Fakhruddin Ali
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/451,089
• Publication Number:
  US 20170178700A1
• Time in Patent Office: 533 Days
• Field of Search: 36518902
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Claims

1. An apparatus, comprising:

a plurality of integrated circuit devices configured to be arranged in one of a plurality of topology configurations, wherein the topology configurations comprise a parallel configuration and a cross parallel configuration; and

one or more switches configured to set the plurality of devices into one of the plurality of topological configuration based on one or more control bits.

2. The apparatus of claim 1, wherein the switches comprise one or more pass-gate switches driven by the one or more control bits.

3. The apparatus of claim 2, wherein the one or more pass-gate switches are driven by the one or more control bits in conjunction with one or more combinational logic circuits.

4. The apparatus of claim 1, wherein the control bits are configured to arrange the plurality of integrated circuit devices into a topology configuration having a least amount of offset voltage.

5. The apparatus of claim 1, wherein a total offset voltage for a particular topology configuration comprises an average of individual offset voltages of the plurality of integrated circuit devices used in the particular topology configuration.