Automated optical inspection of unit specific patterning

• US 10,056,304 B2
• Filed: 05/18/2017
• Issued: 08/21/2018
• Est. Priority Date: 11/19/2014
• Status: Active Grant

• Current Assignee: Deca Technologies USA Inc (Infineon Technologies AG)
• Original Assignee: Deca Technologies Incorporated (Infineon Technologies AG)
• Inventors: Bishop, Craig, Bora, Vaibhav Joga Singh, Scanlan, Christopher M., Olson, Timothy L.
• Primary Examiner(s): Potts, Ryan P
• Application Number:
  US15/599,311
• Publication Number:
  US 20170256466A1
• Time in Patent Office: 460 Days
• Field of Search: None
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/27 : Manufacturing methods
• CPC Class Codes: H01L 2224/29006 : Layer connector larger than the underlying bonding area
• CPC Class Codes: H01L 2224/73153 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/141 : Analog devices
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference standards can be created as a plurality of electrical nets by generating with a computer an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point. An image of each of the plurality of unit specific patterns can be captured with a camera. The image can be processed with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions. Defects in the plurality of unit specific patterns, if present, can be detected by comparing each of the extracted boundaries of contiguous electrically conductive regions to a corresponding one of the plurality of unique reference standards. An output of known good die can be created.

Claims

1. An automated optical inspection (AOI) system, comprising:

aligning a wafer comprising a plurality of unit specific patterns formed on the wafer;

creating a plurality of unique reference standards as a plurality of electrical nets by generating with a computer of the AOI system an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point;

capturing an image of each of the plurality of unit specific patterns on the wafer with a camera;

processing the image with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions;

detecting defects in the plurality of unit specific patterns, if present, by comparing each of the extracted boundaries of contiguous electrically conductive regions to a corresponding one of the plurality of unique reference standards; and

creating an output of known good die from the plurality of unit specific patterns without defects.

2. The AOI system of claim 1, further comprising transforming the start point and the end point of each electrical net by a specified per-package movement, comprising translation, rotation, or both.

3. The AOI system of claim 1, wherein the extracted boundaries of contiguous electrically conductive regions comprise:

a set of polygons;

or

a set of areas of pixels within a set of binary images.

4. The AOI system of claim 3, further comprising:

checking for shorts by verifying that each of the extracted boundaries of contiguous electrically conductive regions contains the start point and the end point for a corresponding electrical net without containing the start point and the end point for other electrical nets; and

checking for minimum line widths and connectivity by eroding boundaries of the plurality of extracted boundaries of contiguous electrically conductive regions by half of a required line width to form extracted and eroded boundaries of contiguous electrically conductive regions and verifying each of the extracted and eroded boundaries of contiguous electrically conductive regions contains the start point and the end point for the corresponding netlists.

5. The AOI system of claim 1, wherein creating the plurality of unique reference standards for each of the plurality of electrical nets further comprises inputting the start point and the end point for adjustable portions of each of the electrical nets into the AOI system.

6. The AOI system of claim 1, wherein the camera captures a plurality of images, each of which is of less than the entire wafer, the plurality of images being stitched together to form the image of the plurality of unit specific patterns that is larger than a size of single camera field.

7. The AOI system of claim 1, wherein the plurality of electrical nets are generated by the computer from a Computer-Aided Design (CAD) file.

8. The AOI system of claim 1, further comprising

a chuck and a stage for aligning the wafer within the AOI system;

and

wherein the computer of the AOI system for generating the start point and the end point and for processing the image to provide a plurality of extracted boundaries of contiguous electrically conductive regions comprises one or more computers, including a computer and a computer server.

9. An automated optical inspection (AOI) system, comprising:

a camera for acquiring an image for each of a plurality of unit specific patterns; and

a computer comprising;

a unique reference standard generator for creating a plurality of unique reference standards as a plurality of electrical nets for each of the plurality of unit specific patterns by generating an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point;

a defect detector for detecting defects in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to the image of the plurality of unit specific patterns, and

an output generator for creating an output of known good die in response to the computer detecting defects.

10. The AOI system of claim 9, further comprising transforming the start point and the end point of each electrical net by one or more specified per-package movements, comprising translation, rotation, or both.

11. The AOI system of claim 9, wherein comparing one of the plurality of unique reference standards to the image of the plurality of unit specific patterns further comprises processing the image with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions, wherein the extracted boundaries of contiguous electrically conductive regions comprise:

a set of polygons;

or

a set of areas of pixels within a set of binary images.

12. The AOI system of claim 9, further comprising:

processing the image of the plurality of unit specific patterns with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions;

checking for shorts by verifying that each of the plurality of extracted boundaries of contiguous electrically conductive regions contains the start point and the end point for a corresponding electrical net without containing the start point and the end point for other electrical nets; and

checking for minimum line widths and connectivity by eroding boundaries of the plurality of extracted boundaries of contiguous electrically conductive regions by half of a required line width to form extracted and eroded boundaries of contiguous electrically conductive regions and verifying each of the extracted and eroded boundaries of contiguous electrically conductive regions contains the start point and the end point for the corresponding net lists.

13. The AOI system of claim 9, wherein the camera captures a plurality of images, each of which is of less than an entire wafer, the plurality of images being stitched together to form the image of the plurality of unit specific patterns that is larger than a size of single camera field.

14. The AOI system of claim 9, further comprising

a chuck and a stage for aligning a wafer comprising the plurality of unit specific patterns within the AOI system;

and

wherein the computer of the AOI system for detecting defects in the plurality of unit specific patterns comprises one or more computers, including a computer and computer servers.

15. The AOI system of claim 14, further comprising a robotic handling system for placing and removing wafers from the chuck, and removing and replacing the wafers before and after inspection.

16. A method of using an automated optical inspection (AOI) system, comprising:

capturing an image of a wafer comprising a plurality of unit specific patterns formed on the wafer to form a captured image;

creating a plurality of unique reference standards as a plurality of electrical nets by generating an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising points;

comparing the captured image of the plurality of unit specific patterns to the plurality of electrical nets to ensure a continuous conductive path between points that should be electrically connected and no conductive path between points that should not be connected.

17. The method of claim 16, wherein the plurality of electrical nets for the plurality of unit specific patterns comprises a start point and an end point for each of the plurality of unit specific patterns.

18. The method of claim 16, further comprising comparing the captured image to the plurality of electrical nets by generating a plurality of extracted boundaries of contiguous electrically conductive regions.

19. The method of claim 16, wherein comparing the captured image to the plurality of electrical nets includes validation of geometric design rules.

20. The method of claim 19, wherein the validation of the geometric design rules comprises at least one of:

validation of trace width, validation of trace spacing, validation of trace length, validation of trace length matching, or validation alignment of package features on different layers within the wafer.