Silicon nitride fill for PC gap regions to increase cell density

• US 10,056,378 B2
• Filed: 11/07/2017
• Issued: 08/21/2018
• Est. Priority Date: 01/26/2015
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Dechao, Liu, Zuoguang, Yamashita, Tenko, Yeh, Chun-Chen
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US15/805,420
• Publication Number:
  US 20180069002A1
• Time in Patent Office: 287 Days
• Field of Search: 438184, 438176, 438195, 438197, 438207, 438196, 257365, 257369, 257390
• CPC Class Codes: H01L 21/02134 the material comprising hydrogen silsesquioxane, e.g. HSQ
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence

Abstract

A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.

Claims

1. A method of fabricating localized isolation between a first gate terminal and a second gate terminal, the method comprising:

providing a semiconductor device, the semiconductor device comprising;

a substrate;

two or more semiconductor fins formed on the substrate; and

one or more gates formed on the two or more semiconductor fins and the substrate;

depositing a flowable oxide layer on the semiconductor device;

etching an area between the two or more semiconductor fins such that the substrate is exposed;

depositing an insulating layer within the etched area; and

removing at least the flowable oxide layer.

2. The method of claim 1, wherein the semiconductor device further comprises:

a hard mask layer present on each of the two or more semiconductor fins.

3. The method of claim 1, wherein the semiconductor device further comprises:

a hard mask layer present on each of the one or more gates.

4. The method of claim 1, further comprising:

removing a portion of the insulating layer present above the top of the flowable oxide layer.

5. The method of claim 1, wherein the insulating layer is comprised of silicon nitride.

6. The method of claim 1, wherein the first gate and the second gate are each comprised of polysilicon.

7. The method of claim 1, wherein the semiconductor device further comprises:

An oxide layer formed on each of the two or more semiconductor fins.

8. A method of fabricating localized isolation between a first gate terminal and a second gate terminal, the method comprising:

providing a semiconductor device, the semiconductor device comprising;

a substrate; and

two or more semiconductor fins formed on the substrate;

depositing a flowable oxide layer on the semiconductor device;

etching an area between the two or more semiconductor fins such that the substrate is exposed;

depositing an insulating layer within the etched area;

removing at least the flowable oxide layer;

forming a first gate over at least a first semiconductor fin of the two or more semiconductor fins; and

forming a second gate over at least a second semiconductor fin of the two or more semiconductor fins.

9. The method of claim 8, wherein the semiconductor device further comprises:

a hard mask layer present on each of the two or more semiconductor fins.

10. The method of claim 8, further comprising:

forming a hard mask layer on the first gate and the second gate.

11. The method of claim 8, wherein the insulating layer is comprised of silicon nitride.

12. The method of claim 8, wherein the first gate and the second gate are each comprised of polysilicon.

13. The method of claim 8, wherein the distance between the first gate and the second gate is less than or equal to ten nanometers.