Enhanced channel strain to reduce contact resistance in NMOS FET devices

• US 10,056,383 B2
• Filed: 03/01/2017
• Issued: 08/21/2018
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Chang, Nieh, Chun-Feng, Chang, Huicheng, Chen, Hou-Yu, Lu, Yong-Yan
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): Rundio, Regan J
• Application Number:
  US15/446,295
• Publication Number:
  US 20170179130A1
• Time in Patent Office: 538 Days
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/26593 at a temperature lower than room temperature
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 : being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 : with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7842 : means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7846 : the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/7855 : with at least two independent gates

Abstract

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Claims

1. A semiconductor device, comprising:

a substrate;

a first fin structure;

a second fin structure;

an isolation layer formed on the substrate, the isolation layer formed adjacent to the first fin structure and the second fin structure;

a first gate structure formed on at least a portion of the first fin structure and the isolation layer;

a second gate structure formed on at least a portion of the second fin structure and the isolation layer;

a first epitaxial layer including a first strained material that provides stress to a channel region of the first fin structure; and

a second epitaxial layer including a second strained material that provides stress to a channel region of the second fin structure, the second epitaxial layer having a first region and a second region, the first region being located closer to a surface of the second epitaxial layer than the second region, the first region having a first doping concentration of a first doping agent and the second region having a second doping concentration of a second doping agent, the first doping concentration being greater than the second doping concentration,

wherein the first doping agent has a first lateral variance and the second doping agent has a second lateral variance, and wherein the first lateral variance is greater than the second lateral variance.

2. The semiconductor device of claim 1, wherein the first doping agent is an n-type dopant comprising phosphorus.

3. The semiconductor device of claim 1, wherein the first region is disposed on the second region, the first region having a thickness in a range from 0.1 nanometers (nm) to 8 nm.

4. The semiconductor device of claim 1, wherein the first doping agent is disposed on a top surface of the second epitaxial layer.

5. The semiconductor device of claim 1, wherein the first strained material is configured for a p-type Fin FET device and the second strained material is configured for an n-type Fin FET device.

6. The semiconductor device of claim 1, wherein the first region has the first doping concentration of a phosphorous dimer dopant and the second region has a second doping concentration of a phosphorous dopant.

7. The semiconductor device of claim 1, wherein the first doping concentration is in a range from 1×

10²¹ atoms/cm³ to 1×

10²² atoms/cm³.

8. The semiconductor device of claim 1, wherein the second doping concentration is in a range from 1×

10¹⁵ atoms/cm³ to 4×

10¹⁵ atoms/cm³.

9. The semiconductor device of claim 1, wherein the first epitaxial layer comprises SiGe.

10. The semiconductor device of claim 1, wherein the second epitaxial layer comprises SiP or SiC.

11. A fin field-effect transistor (Fin FET) semiconductor device, comprising:

a substrate;

a first fin structure having a channel region;

a second fin structure having a channel region;

a first epitaxial layer including a first strained material that provides stress to the channel region of the first fin structure; and

a second epitaxial layer including a second strained material that provides stress to the channel region of the second fin structure,

wherein the second epitaxial layer has a first region and a second region, the first region being located closer to a surface of the second epitaxial layer than the second region,

the first region has a first doping concentration of a first dopant in a range from 1×

10²¹ atoms/cm³ to 1×

10²² atoms/cm³ and the second region has a second doping concentration of a second dopant in a range from 1×

10¹⁵ atoms/cm³ to 4×

10¹⁵ atoms/cm³

wherein the first dopant has a first lateral variance and the second dopant has a second lateral variance, and wherein the first lateral variance is greater than the second lateral variance.

12. The semiconductor device of claim 11, wherein the first epitaxial layer comprises SiGe.

13. The semiconductor device of claim 11, wherein the second epitaxial layer comprises SiP or SiC.

14. The semiconductor device of claim 11, wherein the first region is disposed on the second region, the first region having a thickness in a range from 0.1 nanometers (nm) to 8 nm.

15. The semiconductor device of claim 11, wherein the first doping agent is an n-type dopant comprising phosphorus.

16. A fin field-effect transistor (Fin FET) semiconductor device, comprising:

a substrate;

a first fin structure having a channel region;

a second fin structure having a channel region;

a first epitaxial layer including a first strained material that provides stress to the channel region of the first fin structure; and

a second epitaxial layer including a second strained material that provides stress to the channel region of the second fin structure,

wherein the second epitaxial layer has a first region and a second region, the first region being located closer to a surface of the second epitaxial layer than the second region,

the first region has a first doping concentration of a first dopant and the second region has a second doping concentration of a second dopant,

the first dopant in the first region has a first lateral variance and the second dopant in the second region has a second lateral variance, wherein the first lateral variance is greater than the second lateral variance.

17. The semiconductor device of claim 16, wherein the first region has the first doping concentration of a phosphorous dimer dopant and the second region has the second doping concentration of a phosphorous dopant.

18. The semiconductor device of claim 16, wherein the first epitaxial layer comprises SiGe.

19. The semiconductor device of claim 16, wherein the second epitaxial layer comprises SiP or SiC.

20. The semiconductor device of claim 16, wherein the first region is disposed on the second region, the first region having a thickness in a range from 0.1 nanometers (nm) to 8 nm.