Semiconductor device including write access transistor whose oxide semiconductor layer including channel formation region

• US 10,056,385 B2
• Filed: 02/08/2017
• Issued: 08/21/2018
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US15/427,088
• Publication Number:
  US 20170213832A1
• Time in Patent Office: 559 Days
• Field of Search: 365149, 365145, 365 72, 365 63
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components

Abstract

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Claims

1. A semiconductor device comprising:

a first memory cell;

a second memory cell;

a third memory cell; and

a fourth memory cell,

wherein the first memory cell comprises a first transistor and a second transistor,

wherein the second memory cell comprises a third transistor and a fourth transistor,

wherein the third memory cell comprises a fifth transistor and a sixth transistor,

wherein the fourth memory cell comprises a seventh transistor and an eighth transistor,

wherein each of the first transistor, the third transistor, the fifth transistor and the seventh transistor comprises an oxide semiconductor layer comprising a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein a gate of the third transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor is not directly connected to the other of the source and the drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the fifth transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the eighth transistor,

wherein a gate of the seventh transistor is electrically connected to the second wiring, and

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor.

2. The semiconductor device according to claim 1,

wherein a first insulating layer is over the second transistor, and

wherein the first transistor is over the first insulating layer.

3. The semiconductor device according to claim 2,

wherein a gate electrode of the first transistor is over the first insulating layer,

wherein a second insulating layer is over the gate electrode of the first transistor,

wherein the oxide semiconductor layer of the first transistor is over the second insulating layer, and

wherein a source electrode of the first transistor is over and in contact with the oxide semiconductor layer of the first transistor.

4. The semiconductor device according to claim 2,

wherein a gate electrode of the first transistor is over the first insulating layer,

wherein a second insulating layer is over the gate electrode of the first transistor,

wherein a source electrode of the first transistor is over the second insulating layer, and

wherein the oxide semiconductor layer of the first transistor is over and in contact with the source electrode of the first transistor.

5. The semiconductor device according to claim 2,

wherein the oxide semiconductor layer of the first transistor is over the first insulating layer,

wherein a source electrode of the first transistor is over and in contact with the oxide semiconductor layer of the first transistor,

wherein a second insulating layer is over the source electrode of the first transistor and the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the second insulating layer.

6. The semiconductor device according to claim 2,

wherein a source electrode of the first transistor is over the first insulating layer,

wherein the oxide semiconductor layer of the first transistor is over and in contact with the source electrode of the first transistor and the first insulating layer,

wherein a second insulating layer is over the source electrode of the first transistor and the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the second insulating layer.

7. The semiconductor device according to claim 2,

wherein a bottom surface of a source electrode of the first transistor is over and in contact with a top surface of the first insulating layer,

wherein a bottom surface of a second insulating layer is over and in contact with the top surface of the first insulating layer,

wherein a side surface of the source electrode of the first transistor is in contact with a side surface of the second insulating layer,

wherein the oxide semiconductor layer of the first transistor is over and in contact with a top surface of the source electrode and a top surface of the second insulating layer,

wherein a third insulating layer is over the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the third insulating layer.

8. A semiconductor device comprising:

a first memory cell;

a second memory cell;

a third memory cell; and

a fourth memory cell,

wherein the first memory cell comprises a first transistor, a second transistor and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor and a second capacitor,

wherein the third memory cell comprises a fifth transistor, a sixth transistor and a third capacitor,

wherein the fourth memory cell comprises a seventh transistor, an eighth transistor and a fourth capacitor,

wherein each of the first transistor, the third transistor, the fifth transistor and the seventh transistor comprises an oxide semiconductor layer comprising a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein a first electrode of the first capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the first capacitor is electrically connected to a first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the fourth transistor,

wherein a second electrode of the second capacitor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor is not directly connected to the other of the source and the drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the sixth transistor,

wherein a first electrode of the third capacitor is electrically connected to the gate of the sixth transistor,

wherein a second electrode of the third capacitor is electrically connected to the first wiring,

wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the eighth transistor,

wherein a first electrode of the fourth capacitor is electrically connected to the gate of the eighth transistor,

wherein a second electrode of the fourth capacitor is electrically connected to the second wiring, and

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor.

9. The semiconductor device according to claim 8,

wherein a first insulating layer is over the second transistor, and

wherein the first transistor is over the first insulating layer.

10. The semiconductor device according to claim 9,

wherein a gate electrode of the first transistor is over the first insulating layer,

wherein a second insulating layer is over the gate electrode of the first transistor,

wherein the oxide semiconductor layer of the first transistor is over the second insulating layer, and

wherein a source electrode of the first transistor is over and in contact with the oxide semiconductor layer of the first transistor.

11. The semiconductor device according to claim 9,

wherein a gate electrode of the first transistor is over the first insulating layer,

wherein a second insulating layer is over the gate electrode of the first transistor,

wherein a source electrode of the first transistor is over the second insulating layer, and

wherein the oxide semiconductor layer of the first transistor is over and in contact with the source electrode of the first transistor.

12. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer of the first transistor is over the first insulating layer,

wherein a source electrode of the first transistor is over and in contact with the oxide semiconductor layer of the first transistor,

wherein a second insulating layer is over the source electrode of the first transistor and the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the second insulating layer.

13. The semiconductor device according to claim 9,

wherein a source electrode of the first transistor is over the first insulating layer,

wherein the oxide semiconductor layer of the first transistor is over and in contact with the source electrode of the first transistor and the first insulating layer,

wherein a second insulating layer is over the source electrode of the first transistor and the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the second insulating layer.

14. The semiconductor device according to claim 9,

wherein a bottom surface of a source electrode of the first transistor is over and in contact with a top surface of the first insulating layer,

wherein a bottom surface of a second insulating layer is over and in contact with the top surface of the first insulating layer,

wherein a side surface of the source electrode of the first transistor is in contact with a side surface of the second insulating layer,

wherein the oxide semiconductor layer of the first transistor is over and in contact with a top surface of the source electrode and a top surface of the second insulating layer,

wherein a third insulating layer is over the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the third insulating layer.

15. A semiconductor device comprising:

a first memory cell;

a second memory cell;

a third memory cell; and

a fourth memory cell,

wherein the first memory cell comprises a first transistor, a second transistor and a third transistor,

wherein the second memory cell comprises a fourth transistor, a fifth transistor and a sixth transistor,

wherein the third memory cell comprises a seventh transistor, an eighth transistor and a ninth transistor,

wherein the fourth memory cell comprises a tenth transistor, an eleventh transistor and a twelfth transistor,

wherein each of the first transistor, the fourth transistor, the seventh transistor and the tenth transistor comprises an oxide semiconductor layer comprising a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,

wherein a gate of the third transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the fifth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein a gate of the sixth transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the fifth transistor,

wherein the one of the source and the drain of the second transistor is not directly connected to the other of the source and the drain of the fifth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the eighth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,

wherein a gate of the ninth transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the tenth transistor is electrically connected to a gate of the eleventh transistor,

wherein one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor,

wherein the other of the source and the drain of the eleventh transistor is electrically connected to the other of the source and the drain of the twelfth transistor,

wherein a gate of the twelfth transistor is electrically connected to the second wiring, and

wherein the other of the source and the drain of the eighth transistor is electrically connected to the one of the source and the drain of the eleventh transistor.

16. The semiconductor device according to claim 15,

wherein a first insulating layer is over the second transistor, and

wherein the first transistor is over the first insulating layer.

17. The semiconductor device according to claim 16,

wherein a gate electrode of the first transistor is over the first insulating layer,

wherein a second insulating layer is over the gate electrode of the first transistor,

wherein the oxide semiconductor layer of the first transistor is over the second insulating layer, and

wherein a source electrode of the first transistor is over and in contact with the oxide semiconductor layer of the first transistor.

18. The semiconductor device according to claim 16,

wherein a gate electrode of the first transistor is over the first insulating layer,

wherein a second insulating layer is over the gate electrode of the first transistor,

wherein a source electrode of the first transistor is over the second insulating layer, and

wherein the oxide semiconductor layer of the first transistor is over and in contact with the source electrode of the first transistor.

19. The semiconductor device according to claim 16,

wherein the oxide semiconductor layer of the first transistor is over the first insulating layer,

wherein a source electrode of the first transistor is over and in contact with the oxide semiconductor layer of the first transistor,

wherein a second insulating layer is over the source electrode of the first transistor and the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the second insulating layer.

20. The semiconductor device according to claim 16,

wherein a source electrode of the first transistor is over the first insulating layer,

wherein the oxide semiconductor layer of the first transistor is over and in contact with the source electrode of the first transistor and the first insulating layer,

wherein a second insulating layer is over the source electrode of the first transistor and the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the second insulating layer.

21. The semiconductor device according to claim 16,

wherein a bottom surface of a source electrode of the first transistor is over and in contact with a top surface of the first insulating layer,

wherein a bottom surface of a second insulating layer is over and in contact with the top surface of the first insulating layer,

wherein a side surface of the source electrode of the first transistor is in contact with a side surface of the second insulating layer,

wherein the oxide semiconductor layer of the first transistor is over and in contact with a top surface of the source electrode and a top surface of the second insulating layer,

wherein a third insulating layer is over the oxide semiconductor layer of the first transistor, and

wherein a gate electrode of the first transistor is over the third insulating layer.