Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
First Claim
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1. An integrated circuit comprising:
- a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;
a transistor comprising a source region, a floating body region, a drain region, and a gate;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors;
wherein said transistor is usable to access said memory cell;
wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;
wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and
a control circuit configured to provide electrical signals to said first and second collectors to maintain the states of said memory cells without interrupting access to said memory cells.
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Abstract
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
314 Citations
20 Claims
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1. An integrated circuit comprising:
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a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises; a transistor comprising a source region, a floating body region, a drain region, and a gate; a first bipolar device having a first floating base region, a first emitter, and a first collector; and a second bipolar device having a second floating base region, a second emitter, and a second collector; wherein said first floating base region and said second floating base region are common to said floating body region; wherein said first collector is common to said second collector; wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors; wherein said transistor is usable to access said memory cell; wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line; wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and a control circuit configured to provide electrical signals to said first and second collectors to maintain the states of said memory cells without interrupting access to said memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
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a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises; a transistor comprising a source region, a floating body region, a drain region, and a gate; a first bipolar device having a first floating base region, a first emitter, and a first collector; and a second bipolar device having a second floating base region, a second emitter, and a second collector, wherein said first floating base region and said second floating base region are common to said floating body region; wherein said first collector is common to said second collector; wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell; wherein said transistor is usable to access said memory cell; wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line; wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; wherein at least one of said at least one control line is connected to a read circuitry; wherein states of said memory cells are maintained upon repeated read operations; and a control circuit configured to provide electrical signals to said first and second collectors to maintain the states of said memory cells without interrupting access to said memory cells. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification