Method for fabricating semiconductor device

• US 10,056,388 B2
• Filed: 03/22/2017
• Issued: 08/21/2018
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Original Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Inventors: Lin, Ger-Pin, Wang, Yung-Ming, Chan, Tien-Chen, Chan, Shu-Yen
• Primary Examiner(s): Trinh, Michael
• Application Number:
  US15/465,622
• Publication Number:
  US 20180190660A1
• Time in Patent Office: 517 Days
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a memory region defined thereon;

forming a trench in the substrate;

performing a first ion implantation process to form a first doped region having a first conductive type in the substrate around sidewalls and a bottom surface of the trench, wherein a top surface of the first doped region is higher than a top surface of the substrate;

performing a second ion implantation process to form a lightly doped drain (LDD) having a second conductive type in the substrate before forming the first doped region;

forming a gate electrode in the trench; and

performing a third ion implantation process to form a second doped region having the second conductive type in the substrate above the gate electrode.

2. The method of claim 1, further comprising forming a shallow trench isolation (STI) in the substrate to define the memory region before forming the trench.

3. The method of claim 1, further comprising forming a well region having the first conductive type in the substrate before forming the trench.

4. The method of claim 1, further comprising forming the first doped region in the substrate adjacent to two sides of the trench and in the substrate directly under the trench.

5. The method of claim 1, wherein the gate electrode comprises tungsten.

6. The method of claim 1, wherein a top surface of the gate electrode is lower than a top surface of the first doped region.

7. The method of claim 1, wherein a concentration of the second doped region is higher than a concentration of the first doped region.

8. The method of claim 1, further comprising forming the second doped region in the substrate adjacent to two sides of the trench and above the gate electrode.

9. The method of claim 1, wherein the first conductive type and the second conductive type are different.