Semiconductor device, electrical device system, and method of producing semiconductor device

• US 10,056,424 B2
• Filed: 11/16/2017
• Issued: 08/21/2018
• Est. Priority Date: 02/13/2013
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Kasai, Hiroki
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US15/814,606
• Publication Number:
  US 20180076254A1
• Time in Patent Office: 278 Days
• Field of Search: None
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14676 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/02005 for device characterised by at least one potential jump barrier or surface barrier

Abstract

A semiconductor device includes an SOI substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and an interlayer insulation film formed on the SOI substrate. The SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region. The circuit layer includes a plurality of single pixel circuits arranged in an array pattern. The single pixel circuit includes a circuit element, a diode, and a conductive portion. The diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region. The conductive portion is electrically isolated from other elements. The conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film.

Claims

1. A semiconductor device, comprising:

an SOI (Silicon On Insulation) substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and

an interlayer insulation film formed on the SOI substrate,

wherein said SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region in a plane view,

said circuit layer includes a plurality of single pixel circuits arranged in an array pattern,

each of said single pixel circuits includes a circuit element, a diode, and a conductive portion,

said circuit element is formed on the circuit layer,

said diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region,

said first region has a second conductive type different from the first conductive type,

said conductive portion is electrically isolated from other elements,

said conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film and electrically connected to the second region,

said second region is arranged at a center of each of the single pixel in the plane view, and

said second region has the first conductive type.

2. The semiconductor device according to claim 1, wherein said SOI substrate further includes a substrate contact portion formed in a ring shape and disposed in the outer circumferential region,

said substrate contact portion includes a third region formed on the first semiconductor layer and a second conductive member formed on the interlayer insulation film and electrically connected to the third region, and

said third region has the first conductive type.

3. The semiconductor device according to claim 1, Wherein said first conductive member is connected to the first region through a via passing through the embedded oxide film and the interlayer insulation film, and

said electrode is connected to the second region through a through conductive member passing through the embedded oxide film and the interlayer insulation film.

4. The semiconductor device according to claim 1, wherein each of said single pixel circuits is formed in a substantially rectangular shape, and

said diode is disposed at a corner of the substantially rectangular shape.