Transistor and manufacturing method thereof

• US 10,056,463 B2
• Filed: 06/20/2017
• Issued: 08/21/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Xing, Su, Wang, Hsueh-Wen, Ko, Chien-Yu, Tung, Yu-Cheng, Wang, Jen-Yu, Huang, Cheng-Tung, Lin, Yu-Ming
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US15/628,592
• Publication Number:
  US 20180006129A1
• Time in Patent Office: 427 Days
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors

Abstract

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

Claims

1. A transistor, comprising:

a semiconductor channel layer;

a gate structure disposed on the semiconductor channel layer;

a gate insulation layer disposed between the gate structure and the semiconductor channel layer;

an internal electrode disposed between the gate insulation layer and the gate structure;

a ferroelectric material layer disposed between the internal electrode and the gate structure; and

a spacer disposed on the semiconductor channel layer, wherein a trench surrounded by the spacer is formed above the semiconductor channel layer, the ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench, wherein the gate structure disposed outside the trench overlaps the topmost surface of the ferroelectric material layer, and the ferroelectric material layer comprises a U-shaped structure in the trench.

2. The transistor of claim 1, wherein a thickness of the ferroelectric material layer is larger than a thickness of the gate insulation layer.

3. The transistor of claim 1, wherein the ferroelectric material layer comprises a perovskite oxide material.

4. The transistor of claim 1, wherein the semiconductor channel layer includes indium gallium zinc oxide (IGZO).

5. The transistor of claim 1, wherein the gate insulation layer is disposed in the trench, and the gate insulation layer comprises a U-shaped structure surrounding the ferroelectric material layer in the trench.

6. The transistor of claim 1, wherein the internal electrode is disposed in the trench, and the internal electrode comprises a U-shaped structure surrounding the ferroelectric material layer in the trench.

7. The transistor of claim 1, wherein the gate structure is partly disposed in the trench and partly disposed outside the trench.

8. The transistor of claim 1, wherein the gate structure comprises a metal gate structure.

9. The transistor of claim 1, wherein the gate structure disposed outside the trench overlaps a top surface of the spacer.

10. A manufacturing method of a transistor, comprising:

forming a gate insulation layer on a semiconductor channel layer;

forming an internal electrode on the gate insulation layer;

forming a ferroelectric material layer on the internal electrode;

forming a gate structure on the ferroelectric material layer, wherein at least a part of the ferroelectric material layer is disposed between the gate structure and the internal electrode; and

forming a spacer on the semiconductor channel layer before the step of forming the ferroelectric material layer, wherein a trench surrounded by the spacer is formed above the semiconductor channel layer, and the gate structure is at least partially formed outside the trench, wherein the gate structure formed outside the trench overlaps the topmost surface of the ferroelectric material layer, and the ferroelectric material layer comprises a U-shaped structure in the trench.

11. The manufacturing method of the transistor of claim 10, wherein the step of forming the trench comprises:

forming a dummy gate on the semiconductor channel layer before the step of forming the spacer, wherein the spacer is formed on a side wall of the dummy gate; and

removing the dummy gate for forming the trench surrounded by the spacer.

12. The manufacturing method of the transistor of claim 10, wherein the ferroelectric material layer is formed after the step of forming the trench, and the ferroelectric material layer is formed in the trench.

13. The manufacturing method of the transistor of claim 12, wherein the internal electrode is formed after the step of forming the trench, and the internal electrode is formed in the trench.

14. The manufacturing method of the transistor of claim 13, wherein the internal electrode comprises a U-shaped structure surrounding the ferroelectric material layer in the trench.

15. The manufacturing method of the transistor of claim 13, wherein the gate insulation layer is formed after the step of forming the trench, and the gate insulation layer is formed in the trench.

16. The manufacturing method of the transistor of claim 15, wherein the gate insulation layer comprises a U-shaped structure surrounding the internal electrode in the trench.

17. The manufacturing method of the transistor of claim 10, wherein the gate structure is partly formed in the trench and partly formed outside the trench.

18. The manufacturing method of the transistor of claim 10, wherein the gate structure comprises a metal gate structure.