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Transistor and manufacturing method thereof

  • US 10,056,463 B2
  • Filed: 06/20/2017
  • Issued: 08/21/2018
  • Est. Priority Date: 06/30/2016
  • Status: Active Grant
First Claim
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1. A transistor, comprising:

  • a semiconductor channel layer;

    a gate structure disposed on the semiconductor channel layer;

    a gate insulation layer disposed between the gate structure and the semiconductor channel layer;

    an internal electrode disposed between the gate insulation layer and the gate structure;

    a ferroelectric material layer disposed between the internal electrode and the gate structure; and

    a spacer disposed on the semiconductor channel layer, wherein a trench surrounded by the spacer is formed above the semiconductor channel layer, the ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench, wherein the gate structure disposed outside the trench overlaps the topmost surface of the ferroelectric material layer, and the ferroelectric material layer comprises a U-shaped structure in the trench.

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