Consumption of the channel of a transistor by sacrificial oxidation

• US 10,056,470 B2
• Filed: 01/18/2017
• Issued: 08/21/2018
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Arvet, Christian, Posseme, Nicolas
• Primary Examiner(s): Vinh, Lan
• Application Number:
  US15/408,793
• Publication Number:
  US 20170207320A1
• Time in Patent Office: 580 Days
• Field of Search: 438739, 438735, 438736, 438745, 438753, 438756, 438765, 438738
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for manufacturing a transistor is provided, the transistor including a gate disposed above an underlying layer of a semiconductor material, the gate including at least one first flank and at least one second flank, and a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and the method including forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, and selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.

Claims

1. A method for manufacturing a transistor,

the transistor comprising:

a gate disposed above an underlying layer of a semiconductor material, the gate comprising at least one first flank and at least one second flank, and

a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and

the method comprising;

forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, the selectivity layer being obtained by at least;

transforming at least a portion of a material of the original layer according to a thickness dimension of the original layer and starting from an exposed surface of the original layer so as to form a portion of transformed material configured to not expose the gate foot, and

partially removing at least one portion of the portion of transformed material so as to retain a layer of transformed material forming the selectivity layer above the peripheral portion and so as to expose at least partially the gate foot; and

selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.

2. The method according to claim 1, wherein the transforming comprises a step of oxidizing the portion of the material of the original layer.

3. The method according to claim 1, wherein the selectivity layer has a thickness that is less than a height of the gate foot, so as to allow for lateral access to the gate foot.

4. The method according to claim 1, wherein the transforming provides a thickness of the peripheral portion of the underlying layer that is at least 3 nm.

5. The method according to claim 1, wherein the selective etching is an isotropic etching.

6. The method according to claim 1, wherein a width of the gate is greater than or equal to a width of the gate foot, said widths being taken in a direction perpendicular to a thickness dimension of the underlying layer.

7. The method according to claim 1, further comprising a step of removing the selectivity layer after the selective etching.

8. The method according to claim 7, wherein the step of removing the selectivity layer is performed by at least one wet etching.

9. The method according to claim 1, wherein the forming of the selectivity layer comprises, before the transforming, a step of partially removing the original layer around the gate so as to form a residual portion of the original layer, with the transforming being applied to the residual portion of the original layer.

10. The method according to claim 9, wherein the transforming is anisotropic with a maximum transformation direction directed according to the thickness dimension.

11. The method according to claim 9, wherein the step of partially removing the original layer comprises at least partially deoxidizing at least one of the first and second flanks of the gate foot.

12. The method according to claim 1, further comprising a step of forming at least one spacer, the forming comprising forming a dielectric layer at least partially covering the at least one first flank and the at least one second flank so as to at least partially not cover the gate foot.

13. The method to claim 12, wherein the step of forming the selectivity layer is performed after the step of forming the at least one spacer.

14. The method according to claim 12, further comprising, after the forming of the dielectric layer, a step of removing the dielectric layer from a surface of the original layer.

15. The method according to claim 14, wherein said step of removing is performed so as to leave the at least one first flank and the at least one second flank covered with the dielectric layer in order to form the at least one spacer.

16. The method according to claim 14, wherein said step of removing is performed by dry etching.