Interlayer dielectric for non-planar transistors
First Claim
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1. An integrated circuit (IC) structure, comprising:
- a fin having a source and a drain, wherein the fin comprises silicon;
a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;
a capping structure over the gate electrode, wherein the capping structure comprises silicon and nitrogen;
a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen, and wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer; and
a contact extending through the dielectric layer to one of the source and the drain.
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Abstract
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
62 Citations
11 Claims
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1. An integrated circuit (IC) structure, comprising:
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a fin having a source and a drain, wherein the fin comprises silicon; a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode; a capping structure over the gate electrode, wherein the capping structure comprises silicon and nitrogen; a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen, and wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer; and a contact extending through the dielectric layer to one of the source and the drain. - View Dependent Claims (2, 3, 4, 5)
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6. A method of fabricating an integrated circuit (IC) structure, comprising:
- forming a fin, wherein the fin comprises silicon;
forming a sacrificial transistor gate on the fin;
depositing a sidewall dielectric material layer over the sacrificial transistor gate and the fin;
forming transistor gate sidewalls from a portion of the sidewall dielectric material layer, wherein the transistor gate sidewalls are on opposing sides of the sacrificial transistor gate;
forming a source in the fin on one side of the sacrificial transistor gate;
forming a drain in the fin on an opposing side of the sacrificial transistor gate;
removing the sacrificial transistor gate to form a gate trench between the transistor gate sidewalls, wherein a portion of the fin is exposed;
conformally depositing a gate dielectric adjacent the fin within the gate trench;
depositing conductive gate material within the gate trench;
removing a portion of the conductive gate material to form a recess between the transistor gate sidewalls;
forming a capping structure within the recess, wherein the capping structure comprises silicon and nitrogen;
forming a dielectric layer adjacent the transistor gate sidewalls, wherein the dielectric layer comprises silicon and oxygen; and
densifying the dielectric layer to form an upper portion of the dielectric layer that has a higher density than a lower portion of the dielectric layer;
planarizing the dielectric layer to expose the capping structure; and
forming a contact extending through the dielectric layer to one of the source and the drain. - View Dependent Claims (7, 8, 9, 10, 11)
- forming a fin, wherein the fin comprises silicon;
Specification