Interlayer dielectric for non-planar transistors

• US 10,056,488 B2
• Filed: 01/06/2017
• Issued: 08/21/2018
• Est. Priority Date: 12/06/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Pradhan, Sameer, Luce, Jeanne
• Primary Examiner(s): Manno, Jessica
• Assistant Examiner(s): Alam, Mohammed R
• Application Number:
  US15/400,958
• Publication Number:
  US 20170125596A1
• Time in Patent Office: 592 Days
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

Claims

1. An integrated circuit (IC) structure, comprising:

a fin having a source and a drain, wherein the fin comprises silicon;

a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;

a capping structure over the gate electrode, wherein the capping structure comprises silicon and nitrogen;

a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen, and wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer; and

a contact extending through the dielectric layer to one of the source and the drain.

2. The integrated circuit (IC) structure of claim 1, wherein the capping structure comprises silicon nitride.

3. The integrated circuit (IC) structure of claim 1, wherein the dielectric layer comprises silicon oxide.

4. The integrated circuit (IC) structure of claim 1, wherein the transistor gate is non-planar.

5. The integrated circuit (IC) structure of claim 1, wherein the source and the drain are non-planar.

6. A method of fabricating an integrated circuit (IC) structure, comprising:

forming a fin, wherein the fin comprises silicon;

forming a sacrificial transistor gate on the fin;

depositing a sidewall dielectric material layer over the sacrificial transistor gate and the fin;

forming transistor gate sidewalls from a portion of the sidewall dielectric material layer, wherein the transistor gate sidewalls are on opposing sides of the sacrificial transistor gate;

forming a source in the fin on one side of the sacrificial transistor gate;

forming a drain in the fin on an opposing side of the sacrificial transistor gate;

removing the sacrificial transistor gate to form a gate trench between the transistor gate sidewalls, wherein a portion of the fin is exposed;

conformally depositing a gate dielectric adjacent the fin within the gate trench;

depositing conductive gate material within the gate trench;

removing a portion of the conductive gate material to form a recess between the transistor gate sidewalls;

forming a capping structure within the recess, wherein the capping structure comprises silicon and nitrogen;

forming a dielectric layer adjacent the transistor gate sidewalls, wherein the dielectric layer comprises silicon and oxygen; and

densifying the dielectric layer to form an upper portion of the dielectric layer that has a higher density than a lower portion of the dielectric layer;

planarizing the dielectric layer to expose the capping structure; and

forming a contact extending through the dielectric layer to one of the source and the drain.

7. The method of claim 6, wherein densifying the dielectric layer comprises oxidizing the dielectric layer.

8. The method of claim 6, wherein densifying the dielectric layer comprises annealing the dielectric layer.

9. The method of claim 6, wherein densifying the dielectric layer comprises oxidizing and annealing the dielectric layer.

10. The method of claim 6, wherein forming the capping structure comprises forming a silicon nitride capping structure.

11. The method of claim 6, wherein forming the dielectric layer comprises forming a silicon oxide dielectric layer.