Delay line system and switching apparatus with embedded attenuators
First Claim
1. A monolithically integrated switch comprising:
- an input port configured to carry an input signal;
a plurality of switches configured to provide a plurality of conduction paths;
a first output port and a second output port;
a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches;
a second conduction path of the plurality of conduction paths between the input port and the second output port;
a first shunting path of the plurality of conduction paths between the first output port and a reference potential;
a second shunting path of the plurality of conduction paths between the second output port and the reference potential;
wherein;
a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode of operation of the switch;
during a first mode of operation of the switch, the first conduction path and the second shunting path are low impedance conduction paths, and the second conduction path and the first shunting path are high impedance conduction paths, andduring a second mode of operation of the switch, the second conduction path and the first shunting path are low impedance conduction paths, and the first conduction path and the second shunting path are high impedance conduction paths.
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Accused Products
Abstract
Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators. According to one aspect, a delay line module includes two switches with delay lines coupled between respective output ports of the switches. Each switch includes MOSFET switches forming conduction paths with selectable high and low impedances. According to another aspect, at least one of the conduction paths includes an attenuator block formed by one or more shunting resistors coupled to one of the MOSFET switches. The output ports of the switches can be selectively coupled to a reference ground via a shunted MOSFET switch.
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Citations
35 Claims
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1. A monolithically integrated switch comprising:
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an input port configured to carry an input signal; a plurality of switches configured to provide a plurality of conduction paths; a first output port and a second output port; a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches; a second conduction path of the plurality of conduction paths between the input port and the second output port; a first shunting path of the plurality of conduction paths between the first output port and a reference potential; a second shunting path of the plurality of conduction paths between the second output port and the reference potential; wherein; a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode of operation of the switch; during a first mode of operation of the switch, the first conduction path and the second shunting path are low impedance conduction paths, and the second conduction path and the first shunting path are high impedance conduction paths, and during a second mode of operation of the switch, the second conduction path and the first shunting path are low impedance conduction paths, and the first conduction path and the second shunting path are high impedance conduction paths. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 27, 28, 29)
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14. A monolithically integrated switch comprising:
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an input port configured to carry an input signal; a plurality of switches configured to provide a plurality of conduction paths; a plurality of output ports comprising a first output port, a second output port, . . . , and an nth output port, n being an integer equal to or greater than three; a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches; a second conduction path of the plurality of conduction paths between the input port and the second output port; . . . an nth conduction path of the plurality of conduction paths between the input port and the nth output port; a first shunting path of the plurality of conduction paths between the first output port and a reference potential; a second shunting path of the plurality of conduction paths between the second output port and the reference potential; . . . and; an nth shunting path of the plurality of conduction paths between the nth output port and the reference potential, wherein; a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode i of operation of the switch, where i∈
[1, 2, . . . , n],during the mode i of operation of the switch, the ith conduction path is a low impedance conduction path and all pth conduction paths, with p=[1, 2, . . . , i−
1, i+1, . . . , n], are high impedance conduction paths, andduring the mode i of operation of the switch, the ith shunting path is a high impedance conduction path and all pth shunting paths, with p=[1, 2, . . . , i−
1, i+1, . . . , n], are low impedance conduction paths. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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30. A method for reducing input return loss in a monolithically integrated single pole double throw (SPDT) switch, the method comprising:
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providing in a conduction path between a pole terminal and a first throw terminal of the SPDT integrated switch an attenuator block comprising one or more switches and one or more shunting resistors; based on the providing, selecting a resistance value of the one or more shunting resistors based on an ON resistance of the one or more switches and a desired load impedance at the first throw terminal; based on the selecting, decreasing an impedance value seen at the first throw terminal; and based on the decreasing, substantially matching the impedance value seen at the first throw terminal to the desired load impedance, thereby reducing the input return loss at the first throw terminal. - View Dependent Claims (31)
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32. A monolithically integrated switch comprising:
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(i) an input port configured to carry an input signal; (ii) a first output port and a second output port; (iii) a first conduction path between the input port and the first output port, comprising; a first group of one or more series connected switches coupled between the input port and the first output port; a first group of one or more shunting resistors coupled between the first group of one or more series connected switches and ground; and a second group of one or more series connected switches coupled between the first output port and ground; and (iv) a second conduction path between the input port and the second output port, comprising; a third group of one or more series connected switches coupled between the input port and the second output port; a second group of one or more shunting resistors coupled between the third group of one or more series connected switches and ground; and a fourth group of one or more series connected switches coupled between the second output port and ground. - View Dependent Claims (33, 34, 35)
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Specification