Field programmable gate array utilizing two-terminal non-volatile memory

• US 10,056,907 B1
• Filed: 05/12/2017
• Issued: 08/21/2018
• Est. Priority Date: 07/29/2011
• Status: Active Grant

• Current Assignee: Crossbar Inc.
• Original Assignee: Crossbar Inc.
• Inventors: Asnaashari, Mehdi, Nazarian, Hagop, Nguyen, Sang
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US15/593,371
• Time in Patent Office: 466 Days
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

Claims

1. A field programmable gate array (FPGA), comprising:

a switching block routing array comprising a plurality of signal inputs and a plurality of signal outputs;

a first transistor element coupled to the switching block routing array, wherein the first transistor element comprises a first gate, a first transistor terminal and a second transistor terminal, wherein the first transistor terminal is coupled to a signal input from the plurality of signal inputs, and wherein the second transistor terminal is coupled to a signal output from the plurality of signal outputs, and wherein the first gate is configured to electrically couple or decouple the signal input and the signal output in response to a gate control signal;

a latch comprising a first latch terminal and a second latch terminal, wherein the second latch terminal is coupled to the first gate of the first transistor element;

a second transistor element comprising a second gate, a third transistor terminal and a fourth transistor terminal;

wherein the fourth transistor terminal is coupled to the first latch terminal and the second gate is selectively coupled to an activation voltage;

a plurality of resistive elements coupled to the second transistor element, wherein each resistive element from the plurality of resistive elements comprises a first electrode and a second electrode, wherein each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein the plurality of resistive elements includes a first resistive element and a second resistive element, wherein a first electrode of the first resistive element is selectively coupled to a first voltage source, wherein a second electrode of the second resistive element is selectively coupled to a second voltage source;

a shared node coupled to a second electrode of the first resistive element, to a first electrode of the second resistive element, and to the third transistor terminal of the second transistor element, wherein the plurality of resistive elements are configured to provide a set signal at the shared node in response at least to a first resistive state of the first resistive element, to a second resistive state of the second resistive element, a relatively high voltage from the first voltage source, and a relatively low or ground voltage from the second voltage source, wherein the second transistor element facilitates controlling propagation of the set signal to the latch in response to the activation voltage, and the first latch terminal of the latch is configured to become set with the set signal in response to activation of the second transistor and propagation of the set signal to the latch, and the first transistor element is configured to electrically couple the signal input to the signal output in response to the first latch terminal becoming set with the set signal; and

a programming circuit coupled to the shared node, wherein the programming circuit is configured to facilitate entry to the first resistive state of the first resistive element or is configured to facilitate entry of the second resistive state of the second resistive element in response to an output path voltage applied by the programming circuit to the shared node.

2. The field programmable gate array (FPGA) of claim 1, wherein the plurality of resistive elements are further configured to provide an unset signal at the shared node in response at least to a second resistive state of the first resistive element, to a first resistive state of the second resistive element, the voltage from the first voltage source, and to the voltage from the second voltage source, wherein the second transistor element facilitates controlling propagation of the unset signal to the latch in response to the activation voltage, and first latch terminal of the latch is configured to store the unset signal in response to activation of the second transistor and propagation of the unset signal to the latch, and the first transistor element is further configured to electrically decouple the signal input from the signal output in response to the first latch terminal storing the unset signal.

3. The field programmable gate array (FPGA) of claim 1, wherein the plurality of resistive elements includes a third resistive element and a fourth resistive element, wherein a first electrode of the third resistive element is selectively coupled to a third voltage source, wherein a second electrode of the fourth resistive element is selectively coupled to a fourth voltage source, wherein the plurality of resistive elements are further configured to provide the set signal at the shared node in response at least to a first resistive state of the third resistive element, to a second resistive state of the fourth resistive element, the relatively high voltage from the third voltage source, and the relatively low voltage or ground from the fourth voltage source, and wherein the shared node is further coupled to a second electrode of the third resistive element and a first electrode of the fourth resistive element.

4. The field programmable gate array (FPGA) of claim 3, wherein the programming circuit is further configured to facilitate entry to the first resistive state of the third resistive element or is configured to facilitate entry of the second resistive state of the fourth resistive element in response to an output path voltage applied by the programming circuit to the shared node.

5. The field programmable gate array (FPGA) of claim 3, wherein the plurality of resistive elements are further configured to provide an unset signal at the shared node in response at least to a second resistive state of the third resistive element, to a first resistive state of the fourth resistive element, to the voltage from the third voltage source, and to the voltage from the fourth voltage source, wherein the second transistor element facilitates controlling propagation of the unset signal to the first latch terminal in response to the activation voltage, and the first latch terminal is configured to store the unset signal in response to activation of the second transistor and propagation of the unset signal to the first latch terminal, and the first transistor element is further configured to electrically decouple the signal input from the signal output in response to the first latch terminal storing the unset signal.

6. The field programmable gate array (FPGA) of claim 1, wherein the plurality of resistive elements includes pairs of third resistive elements and fourth resistive elements, wherein for each pair a first electrode of the third resistive element is selectively coupled to a third voltage source, wherein a second electrode of the fourth resistive element is selectively coupled to a fourth voltage source, wherein the plurality of resistive elements are further configured to provide the set signal at the shared node in response at least to one of the pairs of third resistive elements and fourth resistive elements having a first resistive state of the third resistive element, a second resistive state of the fourth resistive element, a voltage from the third voltage source, and a voltage from the fourth voltage source, and wherein the shared node is further coupled to a second electrode of the third resistive element and a first electrode of the fourth resistive element.

7. The field programmable gate array (FPGA) of claim 6, wherein the plurality of resistive elements are further configured to provide an unset signal at the shared node in response at least to the one pair of the third resistive elements and fourth resistive elements having a second resistive state of the third resistive element, a first resistive state of the fourth resistive element, the voltage from the third voltage source, and the voltage from the fourth voltage source, wherein the second transistor element facilitates controlling propagation of the unset signal to the first latch terminal in response to the activation voltage, and the first latch terminal is configured to store the unset signal in response to activation of the second transistor and propagation of the unset signal to the first latch terminal, and the first transistor element is further configured to electrically decouple the signal input from the signal output in response to the first latch terminal storing the unset signal.

8. The field programmable gate array (FPGA) of claim 1, wherein the latch comprises a first invertor cross coupled with a second invertor.

9. The field programmable gate array (FPGA) of claim 1, wherein the latch comprises at least four additional transistor elements.

10. The field programmable gate array (FPGA) of claim 1, further comprising a third transistor element comprising a third gate, a fifth transistor terminal and a sixth transistor terminal;

wherein the fifth transistor terminal is coupled to the second latch terminal, the sixth transistor terminal is coupled to a low voltage, and the third gate is selectively coupled to a reset voltage, wherein the third transistor element facilitates clearing of the latch in response to coupling the third gate to the reset voltage.

11. A configuration bit for a field programmable gate array (FPGA), comprising:

a signal input and a signal output of a switching block routing array of the FPGA;

a first transistor configured to electrically couple or decouple the signal input and the signal output in response to a control signal applied at a gate of the first transistor;

a latch comprising a first latch terminal and a second latch terminal, wherein the second latch terminal is coupled to the gate of the first transistor and provides the control signal to the gate of the first transistor;

a non-volatile storage cell comprising a first resistive switching device and a second resistive switching device sharing a common node;

a second transistor configured to selectively couple or decouple the common node with the first latch terminal in response to an activation voltage, wherein the second transistor is deactivated in response to the activation voltage having a low value, and electrically decouples the common node from the first latch terminal of the latch; and

a programming circuit coupled to the common node and configured to output a low voltage or a high voltage to the common node to facilitate changing a resistance state at least of the first resistive switching device, wherein a signal provided at the common node by the non-volatile storage cell is loaded to the first latch terminal of the latch in part in response to the activation voltage and the selective coupling of the common node with the first latch terminal by the second transistor.

12. The field programmable gate array (FPGA) of claim 11, wherein the first resistive switching device comprises a first terminal connected to a first voltage source, and the second resistive switching device comprises a second terminal connected to a second voltage source, and further wherein a second terminal of the first resistive switching device and a first terminal of the second resistive switching device are connected to the common node, wherein the signal provided at the common node by the non-volatile storage cell is loaded to the first latch terminal of the latch in further part in response to a relatively high voltage at the first voltage source or a relatively low voltage at the second voltage source.

13. The field programmable gate array (FPGA) of claim 12, further comprising a second non-volatile storage cell connected to the common node and at least to a third voltage source, wherein a second signal stored by the second non-volatile storage cell is provided at the common node in response to activation of the third voltage source and deactivation of the first voltage source.

14. The field programmable gate array (FPGA) of claim 13, wherein the programming circuit is further configured to facilitate changing a second resistance state at least of a third resistive switching device of the second non-volatile storage cell, and a value of the second signal stored by the second non-volatile storage cell, in response to output of the low voltage or the high voltage in conjunction with activation of the third voltage source and grounding a fourth resistive switching device of the second non-volatile storage cell.

15. The field programmable gate array (FPGA) of claim 11, wherein power applied to the non-volatile storage cell is deactivated in response to deactivation of the second transistor.

16. The field programmable gate array (FPGA) of claim 15, wherein the first resistive switching device is a two-terminal, non-volatile resistive switching memory device and the second resistive switching device is a third transistor having a drain connected to the common node, a source connected to a voltage source, and a gate connected to a read enable source to facilitate reading a value of the signal provided at the common node.

17. The field programmable gate array (FPGA) of claim 11, wherein the latch comprises a first invertor cross coupled with a second invertor.

18. The field programmable gate array (FPGA) of claim 11, wherein the latch comprises at least four additional transistors.

19. The field programmable gate array (FPGA) of claim 11, further comprising a third transistor having a drain connected to the gate of the first transistor and to the second latch terminal, a source connected to ground, and a gate of the third transistor selectively coupled to a reset voltage, wherein the third transistor facilitates clearing of the latch in response to the reset voltage being coupled to the gate of the third transistor.

20. The field programmable gate array (FPGA) of claim 13, wherein the second non-volatile storage cell comprises a third resistive switching device having a first terminal thereof connected to the third voltage source and a second terminal thereof connected to the common node, and comprises a fourth resistive switching device having a second terminal thereof connected to a fourth voltage source and a first terminal thereof connected to the common node.