High performance phase locked loop
First Claim
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1. A method comprising:
- receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2;
generating a plurality of partial phase error signals, wherein each partial phase error signal is an analog signal generated using a respective charge pump, the respective charge pump receiving respective charge pump control signals generated by a respective comparison between (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal; and
generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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Abstract
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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Citations
20 Claims
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1. A method comprising:
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receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2; generating a plurality of partial phase error signals, wherein each partial phase error signal is an analog signal generated using a respective charge pump, the respective charge pump receiving respective charge pump control signals generated by a respective comparison between (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal; and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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a multi-phase comparator configured to receive N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, the multi-phase comparator comprising; a plurality of partial phase comparators configured to generate a plurality of partial phase error signals, wherein the plurality partial phase comparators comprise respective charge pumps configured to generate each partial phase error signal as an analog signal according to respective charge pump control signals generated by a respective comparison between (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal; and a summation circuit configured to generate a composite phase error signal by summing the plurality of partial phase error signals, the composite phase error signal for adjusting a fixed phase of a local oscillator. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification