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High performance phase locked loop

  • US 10,057,049 B2
  • Filed: 04/21/2017
  • Issued: 08/21/2018
  • Est. Priority Date: 04/22/2016
  • Status: Active Grant
First Claim
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1. A method comprising:

  • receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2;

    generating a plurality of partial phase error signals, wherein each partial phase error signal is an analog signal generated using a respective charge pump, the respective charge pump receiving respective charge pump control signals generated by a respective comparison between (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal; and

    generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

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