First, second divided scan paths, adaptor, generator and compactor circuitry

• US 10,060,977 B2
• Filed: 06/06/2017
• Issued: 08/28/2018
• Est. Priority Date: 03/09/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Britt, Cynthia
• Application Number:
  US15/615,153
• Publication Number:
  US 20170269158A1
• Time in Patent Office: 448 Days
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving

Abstract

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Claims

1. An integrated circuit comprising:

(a) logic circuitry including primary inputs, primary outputs, stimulus leads, and response leads;

(b) scan path circuitry including a scan data input lead, a scan data output lead, and scan cells, each scan cell including;

(i) multiplexer circuitry having a response input connected with one response lead, a scan data input, a scan enable input, and an output; and

(ii) flip-flop circuitry having an input connected with the output of the multiplexer circuitry, a clock input, and a data output coupled with one stimulus bus lead;

(c) a first scan path of serially connected scan cells that is selectably divided into a first part of scan cells and a second part of scan cells, a scan data input of the first scan cell in each part being coupled to the scan data input lead, and each part including an output buffer having a data input coupled with the data output of the last scan cell in the part, a buffer enable input, and a data output coupled with the scan data output lead;

(d) a second scan path of serially connected scan cells that is selectably divided into a first part of scan cells and a second part of scan cells, a scan data input of the first scan cell in each part being coupled to the scan data input lead, and each part including an output buffer having a data input coupled with the data output of the last scan cell in the part, a buffer enable input, and a data output coupled with the scan data output lead;

(e) adaptor circuitry having a first clock lead connected with the clock inputs of the first part of scan cells in the first and second scan paths, and a second clock lead connected with the clock inputs of the second part of scan cells in the first and second scan paths;

(f) a test data generator circuit having control inputs and coupling the scan data input lead of the scan path circuit with the serial data inputs of the first scan path and the serial data inputs of the second scan path; and

(g) a test data compactor circuit having control inputs and coupling the data output of the output buffers of the first scan path and the second scan path to the serial data output lead of the scan path circuit.

2. The integrated circuit of claim 1 in which the adaptor circuitry includes a scan enable lead connected to the scan enable input of all the scan cells.

3. The integrated circuit of claim 1 in which the adaptor circuitry has a first buff enable lead connected with the buffer enable inputs of the first part of scan cells in the first and second scan paths, and a second buffer enable lead connected with the buffer enable inputs of the second part of scan cells in the first and second scan paths.

4. The integrated circuit of claim 1 in which there are equal numbers of scan cells in each part.

5. The circuit of claim 1 in which there are unequal numbers of scan cells in each part.