Column spacer design for a display incorporating a third metal layer

• US 10,061,164 B2
• Filed: 06/20/2016
• Issued: 08/28/2018
• Est. Priority Date: 06/06/2012
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kim, Kyung-Wook, Chang, Shih-Chang, Chen, Cheng, Park, Young-Bae, Zhong, John Z.
• Primary Examiner(s): Dudek, James
• Application Number:
  US15/186,620
• Publication Number:
  US 20160299372A1
• Time in Patent Office: 799 Days
• Field of Search: None
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/12 electrode
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A display that contains a column spacer arrangement which takes advantage of a protrusion on a TFT substrate is provided. One set of column spacers is disposed on top of the protrusion, while a second set of column spacers of substantially the same height as the first set of column spacers are disposed throughout the display. In this way, the display is adequately protected against deformation from external forces while at the same maintaining enough room to allow for a liquid crystal to spread out during the manufacturing process.

Claims

1. A display, comprising:

a color filter layer;

a thin-film transistor layer comprising;

a thin-film transistor;

a gate line;

a data line;

a passivation layer formed over the thin-film transistor that planarizes the thin-film transistor layer;

a metal layer formed on the passivation layer, wherein the metal layer creates a protrusion on the thin-film transistor layer; and

a plurality of common electrodes interposed between the gate line and the metal layer, wherein the metal layer electrically connects the plurality of common electrodes to each other;

a liquid crystal layer interposed between the color filter layer and the thin-film transistor layer; and

a plurality of column spacers formed on the color filter layer, wherein a first column spacer of the plurality of column spacers directly contacts the metal layer.

2. The display of claim 1, wherein the protrusion on the thin-film transistor layer is formed above the thin-film transistor.

3. The display of claim 1, wherein the first column spacer overlaps the common electrode.

4. The display of claim 1, wherein a second column spacer of the plurality of column spacers extends only partially through the liquid crystal layer.

5. The display of claim 1, wherein each column spacer in the plurality of column spacers has an equal height.

6. A method of arranging a plurality of column spacers in a display, the method comprising:

forming a gate line on a thin-film transistor substrate;

forming a thin-film transistor on the thin-film transistor substrate over the gate line;

forming a passivation layer over the thin-film transistor, wherein the passivation layer planarizes the thin-film transistor substrate;

forming a plurality of common electrodes;

forming a metal layer on the passivation layer, wherein the metal layer overlaps the thin-film transistor and forms a protrusion, wherein the plurality of common electrodes are interposed between the metal layer and the gate line, and wherein the metal layer electrically connects the plurality of common electrodes to each other;

disposing a first column spacer of the plurality of column spacers in direct contact with the metal layer; and

disposing a second column spacer of the plurality of column spacers to form a gap between an end of the second column spacer and the passivation layer.

7. The method of claim 6, wherein a height of the first column spacer is equal to a height of the second column spacer.

8. A display, comprising:

a thin-film transistor substrate layer;

a color filter layer;

a layer of liquid crystal material interposed between the thin-film transistor substrate layer and the color filter layer;

a thin-film transistor formed on the thin-film transistor substrate layer, the thin-film transistor comprising;

a gate line formed on the thin-film transistor substrate layer; and

a data line formed over the gate line, wherein the gate line is interposed between the data line and the thin-film transistor substrate layer;

a planarization layer formed over the thin-film transistor, wherein the thin-film transistor is interposed between the planarization layer and the thin-film transistor substrate layer;

a metal layer formed on the planarization layer, wherein the planarization layer is interposed between the metal layer and the thin-film transistor, and wherein the metal layer overlaps the thin-film transistor and forms a protrusion that extends into the layer of liquid crystal material;

a common electrode interposed between the metal layer and the gate line, wherein the metal layer is electrically connected to the common electrode; and

a column spacer interposed between the color filter layer and the thin-film transistor substrate layer, wherein the column spacer overlaps and directly contacts the metal layer.

9. The display of claim 8 further comprising a dielectric layer, wherein the dielectric layer is interposed between the data line and the planarization layer.

10. The display of claim 8 further comprising an additional column spacer, wherein the additional column spacer contacts the color filter layer and extends only partially through the liquid crystal layer.

11. The display of claim 10, wherein a height of the column spacer is substantially equal to a height of the additional column spacer.