Methods and apparatus to configure performance of a solid state drive based on host write bandwidth

• US 10,061,516 B2
• Filed: 09/25/2015
• Issued: 08/28/2018
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Wakchaure, Yogesh B., Guo, Xin, Pelster, David J., Hoffman, Eric L.
• Primary Examiner(s): Giardino, Jr., Mark A
• Application Number:
  US14/866,192
• Publication Number:
  US 20170090752A1
• Time in Patent Office: 1,068 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

Claims

1. An apparatus comprising:

a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate, the first memory and the second memory included in a same memory instance;

a host rate identifier to detect a data transmission capability of a host;

a ratio determiner to determine a ratio based on the data transmission capability of the host, the first write rate, and the second write rate;

a controller to, in response to receiving a request to write data, determine, based on the ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory, the second portion of the data not included in the first portion of the data, the controller to cause the first portion of the data to be written to the first memory, the controller to detect completion of a bursty write period when an amount of data to be written in a write period has dropped below a threshold representing an average amount of data to be written, the controller to, in response to detection of completion of the bursty write period and the first data having been written to the first memory, cause a buffer controller to write the first data to the second memory.

2. The apparatus as disclosed in claim 1, wherein the first memory stores one bit per cell.

3. The apparatus as disclosed in claim 2, wherein the second memory stores multiple bits per cell.

4. The apparatus as disclosed in claim 3, wherein the second memory stores three bits per cell.

5. The apparatus as disclosed in claim 1, wherein the second portion of the data is to be written the second memory to extend a period of increased performance when writing the data by diverting a percentage of the data away from the first memory.

6. The apparatus as disclosed in claim 1, further including the buffer controller to cause the first portion of the data, once written to the first memory, to be written to the second memory.

7. The apparatus as disclosed in claim 1, wherein the controller is further to determine that the first portion of the data is to be written to the second memory when the first memory is full.

8. The apparatus as disclosed in claim 1, wherein the ratio is representative of a percentage of data to be written to the first memory.

9. The apparatus as disclosed in claim 1, further including a write arbiter to write the first portion of the data to the first memory, the write arbiter to write the second portion of the data to the second memory.

10. A method of writing data in a solid state drive, the method comprising:

detecting, by executing an instruction with a processor, a data transmission capability of a host;

determining, by executing an instruction with the processor, a ratio representative of a percentage of data to be written to a first memory of the solid state drive, the ratio based on the data transmission capability of the host, a first write rate of the first memory, and a second write rate of a second memory, the first write rate greater than the second write rate, the first memory and the second memory included in a same memory instance;

in response to receiving a request to write data, determining, based on the ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory, the second portion of the data not included in the first portion of the data;

writing the first portion of the data to the first memory;

detecting completion of a bursty write period when an amount of data to be written in a write period drops below a threshold representing an average amount of data to be written;

causing, in response to the detection of the completion of the bursty write period and the first portion of the data having been written to the first memory, the first portion of the data to be rewritten to the second memory; and

writing the second portion of the data to the second memory.

11. The method as disclosed in claim 10, wherein the first memory stores one bit per cell.

12. The method as disclosed in claim 11, wherein the second memory stores multiple bits per cell.

13. The method as disclosed in claim 12, wherein the second memory stores three bits per cell.

14. The method as disclosed in claim 10, wherein writing the second portion of the data to the second memory extends a period of increased performance when writing the data to the solid state drive by diverting a percentage of the data away from the first memory.

15. The method as disclosed in claim 10, further including determining that the first portion of the data is to be written to the second memory when the first memory is full.

16. A tangible machine-readable storage medium comprising instructions which, when executed, cause a solid state drive to at least:

detect a data transmission capability of a host;

determine a ratio representative of a percentage of data to be written to a first memory of the solid state drive, the ratio based on the data transmission capability of the host, a first write rate of the first memory, and a second write rate of a second memory, the first write rate greater than the second write rate, the first memory and the second memory included in a same memory instance;

in response to receiving a request to write data, determine, based on the ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory, the second portion of the data not included in the first portion of the data;

write the first portion of the data to the first memory;

detect completion of a bursty write period when an amount of data to be written in a write period drops below a threshold representing an average amount of data to be written;

cause, in response to the detection of the completion of the bursty write period and the first portion of the data having been written to the first memory, the first portion of the data to be rewritten to the second memory; and

write the second portion of the data to the second memory.

17. The machine-readable storage medium as disclosed in claim 16, wherein the first memory stores one bit per cell.

18. The machine-readable storage medium as disclosed in claim 17, wherein the second memory stores multiple bits per cell.

19. The machine-readable storage medium as disclosed in claim 16, wherein writing the second portion of the data to the second memory extends a period of increased performance when writing the data to the solid state drive by diverting a percentage of the data away from the first memory.

20. The machine-readable storage medium as disclosed in claim 16, wherein the instructions, when executed, further cause the solid state drive to determine that the first portion of the data is to be written to the second memory when the first memory is full.