Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors

• US 10,061,714 B2
• Filed: 03/18/2016
• Issued: 08/28/2018
• Est. Priority Date: 03/18/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Brown, David A., Jain, Rishabh, Duller, Michael, Idicula, Sam, Schlanger, Erik, Hawkins, David Joseph
• Primary Examiner(s): Sun, Michael
• Application Number:
  US15/073,905
• Publication Number:
  US 20170270052A1
• Time in Patent Office: 893 Days
• Field of Search: None
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data. Based on the descriptor, the first set of electronic circuits determines control information indicating that the one or more data manipulation operations are to be performed on the tabular data and transmits the control information, using a hardware data channel, to a second set of electronic circuits to perform the one or more operations. Based on the control information, the second set of electronic circuits retrieve the tabular data from source memory location and apply the one or more data manipulation operations to generate the data manipulation result. The second set of electronic circuits cause the data manipulation result to be stored at the destination memory location.

Claims

1. A method for moving tabular data to on-chip memory:

in response to a particular memory location being pushed into a first register within a first register space that is accessible by a first set of electronic circuits;

said first set of electronic circuits accessing a descriptor stored at the particular memory location, wherein the descriptor indicates;

a width of a column of tabular data, a number of rows of said column of tabular data, and one or more tabular data manipulation operations to perform on said column of tabular data;

a source memory location for said column of tabular data

a destination memory location for a data manipulation result of said one or more tabular data manipulation operations; and

the first set of electronic circuits determining, based on the descriptor, control information indicating said one or more tabular data manipulation operations to perform on said column of tabular data;

the first set of electronic circuits transmitting, using a hardware data channel, the control information to a second set of electronic circuits to perform the one or more tabular data manipulation operations;

according to the control information, said second set of electronic circuits retrieving said column of tabular data from said source memory location;

applying said one or more tabular data manipulation operations to said column of tabular data to generate said data manipulation result; and

causing said data manipulation result to be stored at said destination memory location.

2. The method of claim 1, wherein the descriptor indicates a type of the descriptor.

3. The method of claim 1, wherein the descriptor indicates a wait condition that should be satisfied prior to the step of the first set of electronic circuits determining the control information.

4. The method of claim 1, further comprising:

the first set of electronic circuits adding the descriptor to a hardware managed linked list;

wherein adding the descriptor to a hardware managed linked list comprises writing the particular memory location to a particular descriptor field of a second descriptor.

5. The method of claim 1, wherein the descriptor indicates automatically incrementing said source memory location and a source counter.

6. The method of claim 5, further comprising:

in response to a second memory location being pushed into the first register;

said first set of electronic circuits accessing a second descriptor stored at the second memory location, wherein the second descriptor indicates;

the source memory location for said column of tabular data;

said second set of electronic circuits determining a new source memory location based at least in part on a value of the source counter.

7. The method of claim 6, further comprising:

said first set of electronic circuits incrementing a source counter value by one after the step of the first set of electronic circuits transmitting the control information to the second set of electronic circuits.

8. The method of claim 1, further comprising:

in response to a second memory location being pushed into the first register;

said first set of electronic circuits accessing a second descriptor stored at the second memory location, wherein the second descriptor indicates;

the particular memory location.

9. The method of claim 8, further comprising:

wherein the second descriptor indicates an iteration count;

the first set of electronic circuits determining that the iteration count is not zero prior to accessing the descriptor stored at the particular memory location.

10. The method of claim 1, wherein the descriptor indicates a notification flag.

11. A method comprising:

a data processing core coupled with a first on-chip memory pushing a particular memory address of a descriptor into a first register within a first register space that is accessible by a first set of electronic circuits that is coupled to said first on-chip memory;

wherein the descriptor indicates a width of a column of tabular data, a number of rows of said column of tabular data, and a data manipulation operation to perform on said column of tabular data;

in response to said particular memory address of said descriptor being pushed into said first register by said data processing core;

the first set of electronic circuits, using the particular memory address in the first register, accessing the descriptor in the first on-chip memory;

the first set of electronic circuits determining, based on the descriptor, control information indicating one or more data manipulation operations to perform;

in response to determining the control information;

the first set of electronic circuits transmitting, using a hardware data channel, the control information to a second set of electronic circuits to perform said one or more data manipulation operations.

12. The method of claim 11, further comprising:

the data processing core determining that said particular memory address is available in a second register within a second register space that is designated to store memory addresses of the first on-chip memory that are free; and

in response to the particular memory address being available in the second register, the data processing core storing the descriptor at the particular memory address.

13. The method of claim 11, further comprising:

wherein the data processing core determines whether a flag, indicating that one or more memory addresses of the first on-chip memory is available in registers within a second register space, is set, wherein the second register space is designated to store memory addresses of the first on-chip memory that are free;

in response to the flag being set;

the data processing core determining that the particular memory address is available in a particular register within the second register space.

14. The method of claim 11, further comprising:

the first set of electronic circuits adding the descriptor to a linked list managed by hardware of a data movement system.

15. The method of claim 14, wherein adding the descriptor to the linked list is performed by specifying in a link address field of the descriptor a memory address of a second descriptor that is different from the descriptor, wherein the second descriptor is in a second register within the first register space.

16. The method of claim 11, wherein the descriptor is a data descriptor that specifies movement of data from one memory to another memory.

17. The method of claim 16, wherein the descriptor indicates a direction in which the movement of data from one memory to another memory occurs.

18. The method of claim 11, wherein the descriptor is a control descriptor that at least specifies configuration information corresponding to one or more registers of the data movement system.

19. The method of claim 11, wherein the descriptor is an auxiliary descriptor that specifies information which assists in processing of another descriptor.

20. The method of claim 11, wherein the data processing core is the only data processing core that can access the first on-chip memory within a data movement system comprising multiple data processing cores.