Fan-out semiconductor package

• US 10,061,967 B2
• Filed: 07/28/2017
• Issued: 08/28/2018
• Est. Priority Date: 08/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Baek, Yong Ho, Cho, Jung Hyun, Kim, Byoung Chan
• Primary Examiner(s): Semenenko, Yuriy
• Application Number:
  US15/663,304
• Publication Number:
  US 20180053036A1
• Time in Patent Office: 396 Days
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: G06V 40/1329 Protecting the fingerprint sensor against damage caused by the finger
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/24155 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/244 : Connecting portions
• CPC Class Codes: H01L 2224/25171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/25175 : Parallel arrangements
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/26 : Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.

Claims

1. A fan-out semiconductor package comprising:

a first connection member having a through-hole;

a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and

a second connection member disposed on the first connection member and the semiconductor chip,

wherein the second connection member includes redistribution layers electrically connected to the connection pads,

at least one of the redistribution layers of the second connection member includes sensor patterns recognizing a fingerprint,

the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer, a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, a second insulating layer disposed on the first insulating layer and covering the second redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

a lower surface of the first redistribution layer has a step with respect to a lower surface of the first insulating layer.

2. The fan-out semiconductor package of claim 1, wherein the sensor patterns include Tx patterns and Rx patterns formed on different layers, and

the Tx patterns and the Rx patterns are disposed in a mesh form.

3. The fan-out semiconductor package of claim 2, wherein a line width of the Tx patterns is greater than that of the Rx patterns, and

an interval between the Tx patterns is smaller than that between the Rx patterns.

4. The fan-out semiconductor package of claim 1, wherein the sensor patterns include Tx patterns and Rx patterns formed on the same layer, and

the Tx patterns and the Rx patterns are alternatively disposed in a diamond form.

5. The fan-out semiconductor package of claim 1, further comprising a passivation layer disposed on the second connection member,

wherein the passivation layer has a dielectric constant greater than that of an insulating layer of the second connection member.

6. The fan-out semiconductor package of claim 1, wherein at least one of the redistribution layers of the second connection member includes an electromagnetic wave blocking pattern.

7. The fan-out semiconductor package of claim 1, wherein the second connection member includes a plurality of insulating layers, and

an insulating layer, most adjacent to the semiconductor chip, of the plurality of insulating layers of the second connection member, has a thickness greater than those of the other insulating layers of the second connection member.

8. The fan-out semiconductor package of claim 1, wherein the second connection member is disposed on the active surface of the semiconductor chip, and

the first connection member is connected to the semiconductor chip by the second connection member.

9. The fan-out semiconductor package of claim 1, further comprising a third connection member including redistribution layers electrically connected to the connection pads,

wherein the second connection member is disposed on the inactive surface of the semiconductor chip,

the third connection member is disposed on the active surface of the semiconductor chip, and

the second connection member and the third connection member are connected to each other by the first connection member.

10. The fan-out semiconductor package of claim 1, further comprising a passive component disposed in the through-hole,

wherein the passive component is electrically connected to the connection pads.

11. A fan-out semiconductor package comprising:

a first connection member having a through-hole;

a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip;

a second connection member disposed on a first side of the first connection member and the semiconductor chip and including redistribution layers; and

connection terminals disposed on a second side of the first connection member and the semiconductor chip opposing the first side, and including one or more connection terminals disposed on a region not overlapping the semiconductor chip in a direction from the first side to the second side,

wherein the connection terminals are electrically connected to the connection pads of the semiconductor chip,

an outermost redistribution layer among the redistribution layers of the second connection member includes sensor patterns for recognizing a fingerprint,

the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer, a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, a second insulating layer disposed on the first insulating layer and covering the second redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

a lower surface of the first redistribution layer has a step with respect to a lower surface of the first insulating layer.

12. The fan-out semiconductor package of claim 11, wherein no semiconductor chip is disposed on a level of the connection terminals.

13. The fan-out semiconductor package of claim 11, wherein the connection terminals are electrically connected to the connection pads of the semiconductor chip at least through the first to third redistribution layers of the first connection member and one or more of the redistribution layers of the second connection member.

14. The fan-out semiconductor package of claim 11, wherein the connection pads of the semiconductor chip face the second connection member.

15. The fan-out semiconductor package of claim 11, further comprising a third connection member including redistribution layers between the semiconductor chip and the connection terminals,

wherein the connection terminals are electrically connected to the connection pads of the semiconductor chip at least through the redistribution layers of the third connection member, and

the connection pads of the semiconductor chip face the third connection member.