Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets

• US 10,062,422 B2
• Filed: 11/23/2016
• Issued: 08/28/2018
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Wingard, Drew E., Chou, Chien-Chun, Hamilton, Stephen W., Swarbrick, Ian Andrew, Vakilotojar, Vida
• Primary Examiner(s): Mercado, Ramon A.
• Application Number:
  US15/359,895
• Publication Number:
  US 20170140800A1
• Time in Patent Office: 643 Days
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

Claims

1. An apparatus, comprising:

an interconnect of an integrated circuit configured to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein flow control logic internal to the interconnect implements an address map with assigned addresses for the target IP cores in the integrated circuit to route the transactions between the target IP cores and initiator IP cores in the integrated circuit, and

an aggregate target of the target IP cores that includes two or more memory channels that are interleaved in an address space for the aggregate target in the address map,

where each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels,

wherein the address map is divided up into two or more regions, each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, the address map including configurable parameters that can be set in a configuration mechanism for each region to flexibly support a configuration of the aggregate target that is dynamically changeable, and the configurable parameters, associated with the regions and memory interleave segments, are configurable to reconfigure memory channel-to-region assignments in order to spread out different requests to be serviced by different memory channels in different regions,

where the configuration mechanism to set the memory channel-to-region assignments is separate from the flow control logic that is configured to route the transactions between the target IP cores and initiator IP cores and to allow multiple transactions from the same thread to be outstanding to multiple channels of an aggregate target at any given time,

where the interconnect connects to the aggregate target,

where the aggregate target connects to at least two or more memory IP cores each containing its own memory controller,

where the flow control logic applies a flow control splitting protocol to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregate target at any given time and the multiple channels in the aggregate target map to IP memory cores having physically different addresses, where the flow control logic internal to the interconnect is configured to maintain request order routed to the target IP core, where the flow control mechanism cooperates with the flow control logic to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregate target at any given time and the multiple channels in the aggregate target map to IP memory cores having physically different addresses, and

where the flow control logic interrogates the address map based on a logical destination address associated with a request to the aggregate target of the interleaved two or more memory channels and determines which memory channels will service the request and how to route the request to the physical IP addresses of each memory channel in the aggregate target servicing that request so that any IP core need not know of the physical IP addresses of each memory channel in the aggregate target.

2. The apparatus of claim 1,

wherein a first memory channel has a first memory interleave segment of a first size controlled by a configurable parameter of a first region in the address map and a second interleave segment of a second size controlled by a configurable parameter of a second region in the address map, and where the configurable parameters allow a dynamically changeable assignment of interleaved memory interleave segments in the aggregate target after the integrated circuit has been manufactured.

3. The apparatus of claim 1,

wherein each memory interleave segment of those memory channels being defined and interleaved in the address space at a defined length bounded by a minimum burst size configured into one or more DRAM devices that form the memory channel and an anticipated maximum DRAM memory page size for the supported configurations of the memory channel, and the transactions include one or more requests and one or more optional responses.

4. The apparatus of claim 1,

wherein the configurable parameter to control the defined length of the memory interleave segments in the address space assigned to a given region is based on an anticipated type of application expected to have transactions with the memory interleave segments in that region,

where a memory controller is external to the interconnect.

5. The apparatus of claim 1,

wherein the configuration parameters in each region may be configured at a configuration time when the configuration of the first aggregate target is dynamically changeable, the configuration time selected from a group consisting of when the hardware is built, programmed in by OS software at run time, physically changed when the device is fabricated by selecting different on-chip pin combinations, changeable after simulations have been run via software, dynamically changed by asserting/de-asserting voltage is carried on particular control lines routed throughout the chip and any combination thereof.

6. The apparatus of claim 1,

wherein a first region in the address map has defined memory interleave segments allocated to that region from a first memory channel that have a configured granularity at a first amount of bytes and a second region in the address map has defined memory interleave segments allocated to that region from the first memory channel that have a configured granularity at a second amount of bytes.

7. The apparatus of claim 1,

wherein each region in the address map may set its own configurable parameter to control the defined length of the memory interleave segments in the address space assigned to that region based on 1) anticipated programs using memory in that region and 2) to take advantage of a principle of locality of a type of anticipated program using the memory in that region,

where at least two or more regions exist in the address map.

8. The apparatus of claim 1,

wherein the configurable configuration parameters flexibly support a multiple channel configuration that is dynamically changeable and enable a single already-designed System-on-a-Chip design to support a wide range of packaging options that use different external memory configurations and to re-configure channel-to-region assignments and interleaving boundaries between channels to better support different modes of operation of a single package.

9. The apparatus of claim 1,

wherein the configuration mechanism for configuring the configuration parameters may be supplied by a designer via number of ways selected from the group consisting of software writing to a register, selecting on-chip pins to set a selectable pin configuration that establishes a configuration mode with the logic tied to the selectable pin configuration, activating dedicated control lines carrying this configuration information so components can reference the configuration parameters on these control lines routed throughout the chip, embedding into read-only memories that are interrogatable by software, mating connections to proper package solder bonds, and any combination thereof.

10. The apparatus of claim 1,

wherein a user may supply configuration parameters for variables selected from the group consisting of 1) list a number of discreet IP memory cores, 2) list a number of regions in an address map, 3) mapping discreet IP memory cores to regions in the address map 4) remove a channel from a region, which then may collapse the system address populated by a remaining channel in that region;

5) reset a channel'"'"'s presence in a region;

     6) alter a system usable space in one or more memory channels in an aggregate target such as even smaller in size/narrower,

     7) alter a defined size granularity of memory interleave segments;

     8) determine the number of channels in one region, and reassign channels from one region to another, which all will reset an interleaving boundary, have some regions with channels and other regions with no channels and

     9) any combination thereof.

11. The apparatus of claim 1,

wherein configuration logic cooperating with the received configuration parameters limits an amount of legal configurations with the memory system from general purpose to several application specific purposes to limit an amount of configurable parameters that must be communicated and to limit an amount of the logic and hardware physically present on chip to make the memory general purpose for all applications.

12. The apparatus of claim 1, further comprising:

a table maintained locally in each agent receives the region'"'"'s configuration parameter values from a central source of configuration parameters to allow dynamic re-configuration of a multiple channel aggregate target,

one or more initiator agents respectively corresponding to the one or more initiator IP cores configured to interface with the interconnect and interrogate the address map;

one or more target agents respectively corresponding to the one or more target IP cores configured to interface with the interconnect; and

one or more thread splitter units in or near the initiator agents, one or more thread merger units in or near the target agents, or a combination thereof, optionally in a centralized merger-splitter unit.

13. The apparatus of claim 1, further comprising:

a single central configuration register from a user interface perspective exists for a designer to program configuration parameters into this register and the register fields of the central configuration register are configured as export constants.

14. A non-transitory machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to generate a representation of the apparatus of claim 1.

15. The machine-readable medium of claim 14,

wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to generate the representation of the apparatus.

16. The machine-readable medium of claim 14,

wherein a number of channels in an address region is configurable at run time and a first address region and a second address region both map to contain a first channel.

17. A method, comprising:

mapping address regions onto one or more aggregate target Intellectual Property (IP) cores in a group of target IP cores,

wherein an aggregate target includes two or more channels that are interleaved in an address space for the first aggregate target in an address map,

where each channel is divided up in defined interleave segments and then interleaved with interleave segments from other channels,

where transactions are routed over an interconnect between the target IP cores and one or more initiator IP cores according to flow control logic internal to the interconnect that implements an address map located in the interconnect with assigned addresses for the target IP cores,

wherein the address map is divided up into two or more address regions;

configuring parameters associated with the address regions and the interleave segments that can be set for each region to flexibly support a configuration of the aggregate target that is dynamically changeable,

wherein the configuration parameters in each address region is configurable after manufacture of the integrate circuit to reconfigure memory channel-to-region assignments; and

configuring a first interleave segment to a first size controlled by a configurable parameter of a first address region in the address map and configuring a second interleave segment to a second size controlled by a configurable parameter of a second address region in the address map,

wherein each interleave segment of those channels being defined and interleaved in the address space of the regions at a size granularity chosen by a designer and independent of the size granularity of memory interleave segment selected in the other address region, and the size granularity differs between a first region and a second region,

where the interconnect connects to the aggregate target,

where the aggregate target connects to at least two or more memory IP cores each containing its own memory controller,

where the flow control logic applies a flow control splitting protocol to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregate target at any given time and the multiple channels in the aggregate target map to IP memory cores having physically different addresses, where the flow control logic internal to the interconnect is configured to maintain request order routed to the target IP core, where the flow control mechanism cooperates with the flow control logic to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregate target at any given time and the multiple channels in the aggregate target map to IP memory cores having physically different addresses, and

where the flow control logic interrogates the address map based on a logical destination address associated with a request to the aggregate target of the interleaved two or more memory channels and determines which memory channels will service the request and how to route the request to the physical IP addresses of each memory channel in the aggregate target servicing that request so that any IP core need not know of the physical IP addresses of each memory channel in the aggregate target.

18. The method of claim 17,

wherein the configuration parameters in each address region is configurable at the time selected from the group consisting of when the hardware is built, programmed in by Operating System driver software at run time, programmed in through electronic design software at design time, physically changed when the device is fabricated or tested by selecting different on-chip pin combinations, changed after simulations have been run via software, dynamically changed by setting voltage levels on external signal pins and any combination thereof, and the channels are memory channels with memory interleave segments.

19. The method of claim 18,

controlling flow of the transactions with a flow control splitting protocol, thereby enabling the transactions from a same thread to be outstanding to the two or more channels of the aggregate target of the target IP cores at any given time,

wherein one or more initiator agents respectively correspond to the one or more initiator IP cores, the one or more initiator agents configured to interface with the interconnect and interrogate the address map,

wherein one or more target agents respectively corresponding to the one or more target IP cores, the one or more target agents configured to interface with the interconnect,

wherein one or more thread splitter units in or near the initiator agents, one or more thread merger units in or near the target agents, or a combination thereof, optionally in a centralized merger-splitter unit, cooperate with the flow control splitting protocol, and

wherein a user may supply configuration parameters for variables selected from the group consisting of 1) list a number of discreet IP memory cores, 2) list a number of regions in the address map, 3) mapping discreet IP memory cores to regions in the address map 4) remove a channel from a region, which then may collapse the system address populated by a remaining channel in that region;

5) reset a channel'"'"'s presence in a region;

     6) alter a system usable space in one or more memory channels in an aggregate target such as even smaller in size/narrower,

     7) alter a defined size granularity of memory interleave segments;

     8) determine the number of channels in one region, and reassign channels from one region to another, which all will reset an interleaving boundary, have some regions with channels and other regions with no channels and

     9) any combination thereof.

20. An Integrated Circuit, comprising:

one or more initiator IP cores;

multiple target IP cores including memory IP cores;

an interconnect to communicate transactions between the one or more initiator IP cores and the multiple target IP cores coupled to the interconnect,

wherein flow control logic internal to the interconnect implements the address map with assigned address for target IP cores in the integrated circuit to route the requests between the target IP cores and initiator IP cores in the integrated circuit and an aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the aggregate target in the address map,

where each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels,

wherein the address map may be divided up into two or more regions, each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region,

where the configurable address map has configurable parameters that can be set for each region to flexibly support a configuration of the first aggregate target that is dynamically changeable, and the configurable parameters, associated with the regions and memory interleave segments, are configurable to reconfigure memory channel-to-region assignments, and a first region in the address map has defined memory interleave segments allocated to that region from a first memory channel that have a configured size granularity at a first amount of bytes and a second region in the address map has defined memory interleave segments allocated to that region from the first memory channel that have a configured granularity at a second amount of bytes,

where the interconnect connects to the aggregate target,

where the aggregate target connects to at least two or more memory IP cores each containing its own memory controller,

where the flow control logic applies a flow control splitting protocol to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregate target at any given time and the multiple channels in the aggregate target map to IP memory cores having physically different addresses, where the flow control logic internal to the interconnect is configured to maintain request order routed to the target IP core, where the flow control mechanism cooperates with the flow control logic to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregate target at any given time and the multiple channels in the aggregate target map to IP memory cores having physically different addresses, and

where the flow control logic interrogates the address map based on a logical destination address associated with a request to the aggregate target of the interleaved two or more memory channels and determines which memory channels will service the request and how to route the request to the physical IP addresses of each memory channel in the aggregate target servicing that request so that any IP core need not know of the physical IP addresses of each memory channel in the aggregate target.