Low standby power with fast turn on for non-volatile memory devices

• US 10,062,423 B2
• Filed: 09/16/2016
• Issued: 08/28/2018
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Zonte, Cristinel, Raghavan, Vijay, Gradinariu, Iulian C., Moscaluk, Gary Peter, Bettman, Roger, Argrawal, Vineet, Leshner, Samuel
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/268,315
• Publication Number:
  US 20170098468A1
• Time in Patent Office: 711 Days
• Field of Search: 365226, 365227, 365228, 365229, 36518523, 36523006
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Claims

1. A non-volatile memory system comprising:

a memory array;

a plurality of data write circuits coupled to the memory array;

a plurality of data read circuits coupled to the memory array; and

a plurality of drivers coupled to the memory array, the plurality of drivers operatively controlled by a bias control circuit in response to a standby detection signal and an output of a wake-up detection circuit,

wherein the plurality of drivers includes a plurality of distributed analog drivers coupled to the plurality of data read circuits.

2. The non-volatile memory system of claim 1, further comprising a voltage booster circuit coupled to the memory array and operatively controlled by the bias control circuit, the voltage booster circuit to provide a supply voltage to the plurality of data read circuits in a low voltage condition.

3. The non-volatile memory system of claim 2, further comprising a charge pump operatively controlled by the voltage booster, the charge pump to provide a voltage to the voltage booster circuit for use in a low voltage condition.

4. The non-volatile memory system of claim 3, further comprising a frequency divider coupled to the bias control circuit and the voltage booster, the frequency divider to provide a reduced frequency voltage signal to the voltage booster and to the data read circuits.

5. The non-volatile memory system of claim 1, wherein the plurality of drivers comprises a plurality of distributed analog drivers to provide driving voltages with reduced current to the data read circuits.