Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology

• US 10,062,634 B2
• Filed: 12/21/2016
• Issued: 08/28/2018
• Est. Priority Date: 12/21/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsley, Thomas H.
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US15/386,343
• Publication Number:
  US 20180174943A1
• Time in Patent Office: 615 Days
• Field of Search: 257713
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.

Claims

1. A semiconductor die assembly, comprising:

a plurality of first semiconductor dies;

a package substrate underlying the plurality of first semiconductor dies when the semiconductor die assembly is in a given orientation;

an interposer between the package substrate and the plurality of first semiconductor dies, wherein the interposer has a first major surface and a second major surface opposite to its first major surface, wherein a first one of the plurality of first semiconductor dies is electrically coupled to the interposer via the first major surface of the interposer, and wherein a second one of the plurality of first semiconductor dies is electrically coupled to the interposer via the second major surface of the interposer;

a second semiconductor die between the package substrate and the interposer, wherein the second semiconductor die is closer to the second major surface of the interposer than to the first major surface of the interposer; and

a heat spreader configured to transfer heat away from the first and second semiconductor dies, wherein the heat spreader includes—

a cap thermally coupled to the first one of the first semiconductor dies at a first elevation when the semiconductor die assembly is in the given orientation, and

a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation when the semiconductor die assembly is in the given orientation, wherein the interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.

2. The semiconductor die assembly of claim 1 wherein:

the interposer defines an opening; and

the pillar extends through the opening.

3. The semiconductor die assembly of claim 1 wherein the interposer is shaped as a rectangular annulus in the plane between the first and second elevations.

4. The semiconductor die assembly of claim 1 wherein:

the first one of the plurality of first semiconductor dies is a memory die; and

the second semiconductor die is a logic die.

5. The semiconductor die assembly of claim 1 wherein:

the heat spreader includes fins configured to transfer heat by convection; and

the fins are above the pillar when the semiconductor die assembly is in the given orientation.

6. The semiconductor die assembly of claim 1 wherein the cap and the pillar are contiguous components of the heat spreader.

7. The semiconductor die assembly of claim 1 wherein:

the first one of the plurality of first semiconductor dies is laterally spaced apart from the pillar in a first direction; and

the second one of the plurality of first semiconductor dies is laterally spaced apart from the pillar in a second direction opposite to the first direction.

8. The semiconductor die assembly of claim 1 wherein the cap and the pillar are noncontiguous components of the heat spreader.

9. The semiconductor die assembly of claim 8 wherein the cap extends around at least 75% of a perimeter of the pillar at the first elevation.

10. The semiconductor die assembly of claim 1 further comprising:

a first thermal interface feature through which the cap is thermally coupled to the first one of the plurality of first semiconductor dies at the first elevation; and

a second thermal interface feature through which the pillar is thermally coupled to the second semiconductor die at the second elevation.

11. The semiconductor die assembly of claim 10 wherein the first and second thermal interface features are, respectively, first and second pieces of thermal interface tape.

12. The semiconductor die assembly of claim 10 wherein the first and second thermal interface features are, respectively, first and second volumes of thermal interface paste.

13. The semiconductor die assembly of claim 1 wherein:

the package substrate has—

a first major surface, and

a second major surface opposite to its first major surface;

the plurality of first semiconductor dies is closer to the first major surface of the package substrate than to the second major surface of the package substrate;

the semiconductor die assembly further comprises heat transfer material at the first major surface of the package substrate; and

the heat transfer material is thermally coupled to the second one of the plurality of first semiconductor dies.

14. The semiconductor die assembly of claim 13 wherein the heat transfer material is a metal film overlying the package substrate when the semiconductor die assembly is in the given orientation.

15. The semiconductor die assembly of claim 13 wherein:

the heat transfer material includes a peripheral portion extending laterally beyond an edge portion of the interposer when the semiconductor die assembly is in the given orientation;

the semiconductor die assembly further comprises fins thermally coupled to the heat transfer material at the peripheral portion of the heat transfer material; and

the fins are configured to transfer heat by convection.

16. The semiconductor die assembly of claim 13 further comprising a thermal interface feature through which the heat transfer material is thermally coupled to the second one of the plurality of first semiconductor dies.

17. The semiconductor die assembly of claim 16 wherein the thermal interface feature is a piece of thermal interface tape.

18. The semiconductor die assembly of claim 16 wherein the thermal interface feature is a volume of thermal interface paste.

19. A method for making a semiconductor die assembly, the method comprising:

electrically coupling a first one of a plurality of first semiconductor dies to an interposer, wherein the interposer has a first major surface and a second major surface opposite to its first major surface, wherein electrically coupling the first one of the plurality of first semiconductor dies to the interposer includes electrically coupling the first one of the plurality of first semiconductor dies to the interposer via the first major surface of the interposer;

electrically coupling a second one of the plurality of first semiconductor dies to the interposer via the second major surface of the interposer;

electrically coupling a second semiconductor die to a package substrate, wherein the second semiconductor die is closer to the second major surface of the interposer than to the first major surface of the interposer;

the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;

electrically coupling the first one of the plurality of first semiconductor dies to the interposer includes electrically coupling the first one of the plurality of first semiconductor dies to the interposer via the first major surface of the interposer; and

the method further comprises electrically coupling a second one of the plurality of first semiconductor dies to the interposer via the second major surface of the interposer,

electrically coupling the interposer to the package substrate;

thermally coupling a cap of a heat spreader to the first one of the first semiconductor dies, wherein the heat spreader is configured to transfer heat away from the first one of the first semiconductor dies via the cap;

locating a pillar of the heat spreader relative to the interposer such that the interposer extends around at least 75% of a perimeter of the pillar, wherein the heat spreader is configured to transfer heat away from the second semiconductor die via the pillar; and

thermally coupling the pillar to the second semiconductor die.

20. The method of claim 19 wherein:

the interposer defines an opening; and

locating the pillar relative to the interposer includes extending the pillar through the opening.

21. The method of claim 19 wherein:

electrically coupling the first one of the plurality of first semiconductor dies to the interposer includes electrically coupling the first one of the plurality of first semiconductor dies to the interposer at a portion of the interposer laterally spaced apart from the pillar in a first direction; and

the method further comprises electrically coupling the second one of the plurality of first semiconductor dies to the interposer at a portion of the interposer laterally spaced apart from the pillar in a second direction opposite to the first direction.

22. The method of claim 19, further comprising:

disposing a first thermal interface feature in direct contact with the first one of the plurality of first semiconductor dies; and

disposing a second thermal interface feature in direct contact with the second semiconductor die,

wherein—

thermally coupling the cap to the first one of the first semiconductor dies includes thermally coupling the cap to the first one of the first semiconductor dies via the first thermal interface feature, and

thermally coupling the pillar to the second semiconductor die includes thermally coupling the pillar to the second semiconductor die via the second thermal interface feature.

23. The method of claim 22 wherein disposing the first and second thermal interface features includes attaching, respectively, first and second pieces of thermal interface tape.

24. The method of claim 22 wherein disposing the first and second thermal interface features includes depositing, respectively, first and second volumes of thermal interface paste.

25. The method of claim 19 wherein:

the package substrate has—

a first major surface, and

a second major surface opposite to its first major surface;

the plurality of first semiconductor dies is closer to the first major surface of the package substrate than to the second major surface of the package substrate;

the method further comprises thermally coupling a heat transfer material to the second one of the plurality of first semiconductor dies; and

the heat transfer material is at the first major surface of the package substrate.

26. The method of claim 25, further comprising disposing a thermal interface feature in direct contact with the second one of the plurality of first semiconductor dies, wherein thermally coupling the heat transfer material to the second one of the plurality of first semiconductor dies includes thermally coupling the heat transfer material to the second one of the plurality of first semiconductor dies via the thermal interface feature.

27. The method of claim 26 wherein disposing the thermal interface feature includes attaching a piece of thermal interface tape.

28. The method of claim 26 wherein disposing the thermal interface feature includes depositing a volume of thermal interface paste.

29. A method for operating a semiconductor die assembly, the method comprising:

operating a first one of a plurality of first semiconductor dies electrically coupled to an interposer, wherein the interposer has a first major surface and a second major surface opposite to its first major surface, wherein the first one of the plurality of the first semiconductor dies is electrically coupled to the interposer via the first major surface of the interposer;

operating a second one of the plurality of first semiconductor dies electrically coupled to the interposer, wherein the second one of the plurality of first semiconductor dies is electrically coupled to the interposer via the second major surface of the interposer;

operating a second semiconductor die electrically coupled to a package substrate, wherein the second semiconductor die is closer to the second major surface of the interposer than to the first major surface of the interposer, wherein the package substrate has a first major surface and a second major surface opposite to its first major surface, and wherein the first one of the plurality of first semiconductor dies is closer to the first major surface of the package substrate than to the second major surface of the package substrate;

transferring at least 50% of total heat generated by operating the first one of the plurality of first semiconductor dies away from the first one of the plurality of first semiconductor dies via a cap of a heat spreader thermally coupled to the first one of the plurality of first semiconductor dies;

transferring at least 50% of total heat generated by operating the second semiconductor die away from the second semiconductor die via a pillar of the heat spreader thermally coupled to the second semiconductor die and via an opening defined by the interposer, wherein the pillar extends through the opening, and

transferring at least 50% of total heat generated by operating the second one of the plurality of first semiconductor dies away from the second one of the plurality of first semiconductor dies via a heat transfer material thermally coupled to the second one of the plurality of first semiconductor dies, wherein the heat transfer material is at the first major surface of the package substrate.

30. The method of claim 29 wherein the total heat generated by operating the first one of the plurality of first semiconductor dies is at most 25% of the total heat generated by operating the second semiconductor die.