Semiconductor device with buried metallic region, and method for manufacturing the semiconductor device

• US 10,062,757 B2
• Filed: 08/29/2016
• Issued: 08/28/2018
• Est. Priority Date: 02/25/2016
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Toia, Fabrizio Fausto Renzo, Contiero, Claudio, Pizzi, Elisabetta, Mariani, Simone Dario
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Booker, Vicki B
• Application Number:
  US15/250,638
• Publication Number:
  US 20170250253A1
• Time in Patent Office: 729 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

Claims

1. A method for manufacturing an electronic device, comprising:

forming a buried cavity in a semiconductor body;

forming an active region, including an electronic component, in the semiconductor body above the buried cavity;

forming a dielectric region, surrounding the active region, in the semiconductor body;

etching selective portions of the semiconductor body and the dielectric region to form one or more openings in fluidic connection with the buried cavity;

depositing metallic material within the buried cavity through the one or more openings, completely coating internal walls of the buried cavity and forming a metallic buried region, and completely coating internal walls of the one or more openings to form one or more paths for electrical access to the metallic buried region, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, and forming the buried cavity includes;

etching selective portions of the substrate and forming a recess;

filling the recess with silicon germanium to form a sacrificial layer of silicon germanium;

growing an epitaxial layer on the substrate and on the sacrificial layer; and

removing completely the sacrificial layer through said one or more openings.

2. The method according to claim 1, wherein the depositing includes depositing the metallic material using CVD and/or ALD technology.

3. The method according to claim 1, further comprising, prior to depositing the metallic material, depositing a barrier layer configured to form a barrier against diffusion of metallic species towards the semiconductor body and to form an ohmic contact with the substrate.

4. The method according to claim 1, wherein coating the internal walls of the buried cavity and of coating the internal walls of the one or more openings are carried out simultaneously.

5. The method according to claim 1, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, wherein the substrate has a first conductivity, the method further comprising:

implanting dopant species that have a second conductivity type in the substrate, thereby forming an implanted region; and

forming the buried cavity inside the implanted region and/or the epitaxial layer so that the metallic buried region is separated from a portion of the substrate by a portion of the implanted region and/or of the epitaxial layer.

6. The method according to claim 1, wherein forming the dielectric region and forming the one or more openings occur after forming the buried cavity in the semiconductor body.

7. A method for manufacturing an electronic device, comprising:

forming a buried cavity in a semiconductor body;

forming an active region, including an electronic component, in the semiconductor body above the buried cavity;

forming a dielectric region, surrounding the active region, in the semiconductor body, after forming the buried cavity;

etching selective portions of the semiconductor body at the dielectric region after forming the buried cavity, the etching step forming one or more openings in fluidic connection with the buried cavity;

depositing metallic material within the buried cavity through the one or more openings, completely coating internal walls of the buried cavity and forming a metallic buried region, and completely coating internal walls of the one or more openings to form one or more paths for electrical access to the metallic buried region, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, and forming the buried cavity includes;

etching selective portions of the substrate and forming a recess;

filling the recess with silicon germanium to form a sacrificial layer of silicon germanium;

growing an epitaxial layer on the substrate and on the sacrificial layer; and

removing completely the sacrificial layer through, said one or more openings.

8. The method according to claim 7, further comprising, prior to depositing the metallic material, depositing a barrier layer configured to form a barrier against diffusion of metallic species towards the semiconductor body and to form an ohmic contact with the substrate.

9. The method according to claim 7, wherein coating the internal walls of the buried cavity and of coating the internal walls of the one or more openings are carried out simultaneously.

10. The method according to claim 7, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, wherein the substrate has a first conductivity, the method further comprising:

implanting dopant species that have a second conductivity type in the substrate, thereby forming an implanted region; and

forming the buried cavity inside the implanted region and/or the epitaxial layer so that the conductive buried region is separated from a portion of the substrate by a portion of the implanted region and/or of the epitaxial layer.

11. The method according to claim 7, wherein forming the one or more openings includes etching selective portions of the dielectric region.

12. A method for manufacturing an electronic device, comprising:

etching selective portions of a semiconductor substrate and forming a recess;

filling the recess with silicon germanium to form a sacrificial layer of silicon germanium;

growing an epitaxial layer on the substrate and on the sacrificial layer;

forming an electronic component in the epitaxial layer and above the sacrificial layer;

forming a dielectric region surrounding the active region and above the epitaxial layer and sacrificial layer;

etching selective portions of the semiconductor body and the dielectric region, the etching step forming one or more openings in fluidic connection with the buried cavity;

removing completely the sacrificial layer through said one or more openings, forming a buried cavity in the substrate; and

depositing metallic material within the buried cavity through the one or more openings, completely coating internal walls of the buried cavity and forming a metallic buried region, and completely coating internal walls of the one or more openings to form one or more paths for electrical access to the conductive buried region.

13. The method according to claim 12, further comprising, prior to depositing the metallic material, depositing a barrier layer configured to form a barrier against diffusion of metallic species towards the semiconductor body and to form an ohmic contact with the substrate.

14. The method according to claim 12, wherein coating the internal walls of the buried cavity and of coating the internal walls of the one or more openings are carried out simultaneously.