Semiconductor device

• US 10,062,758 B2
• Filed: 08/19/2014
• Issued: 08/28/2018
• Est. Priority Date: 04/26/2010
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Miura, Naruhisa, Nakata, Shuhei, Ohtsuka, Kenichi, Watanabe, Shoyu, Watanabe, Hiroshi
• Primary Examiner(s): Niesz, Jamie C
• Application Number:
  US14/463,286
• Publication Number:
  US 20140353686A1
• Time in Patent Office: 1,470 Days
• Field of Search: 257 77
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a semiconductor layer on a surface of said semiconductor substrate;

a source electrode on a surface of said semiconductor layer;

a drain electrode on a rear surface of said semiconductor substrate; and

a gate electrode forming a channel region in said semiconductor layer;

wherein said semiconductor layer comprises;

a first conductivity region on said surface of said semiconductor substrate;

a plurality of first well regions of a second conductivity type on said first conductivity region, facing said gate electrode with an insulating film therebetween;

a source region of the first conductivity type in a surface region of each of said first well regions, connected to said source electrode; and

a second well region of the second conductivity type in said semiconductor layer which is vertically overlapped by the gate electrode, the second well region of the second conductivity type in said semiconductor layer overlapping the drain electrode,

wherein a second conductivity type impurity concentration profile of said second well region includes a maximum value point, which is at a position which is not vertically overlapped by the first well region, which is deeper than a surface of said second well region between said gate electrode and said drain electrode, and

wherein a second conductivity type impurity concentration of the maximum value point is at least ten times greater than a second conductivity type impurity concentration of the surface of said second well region.

2. The semiconductor device according to claim 1,

wherein said maximum value point is located at a depth of 0.3 μ

m to 1.0 μ

m from the surface of said semiconductor layer.

3. The semiconductor device according to claim 1,

wherein said maximum value point is located deeper than said surface of said semiconductor layer.

4. The semiconductor device according to claim 3,

wherein said maximum value point is located at a depth less than 0.7 μ

m from the surface of said semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the second impurity type concentration of said second well region is in a range between 1×

10¹⁵ cm<sup>−

3</sup> and 1×

10²¹ cm<sup>−

3</sup>.

6. The semiconductor device according to claim 5,

wherein the second impurity type concentration of said second well region is in a range between 1×

10¹⁶ cm<sup>−

3</sup> and 1×

10¹⁹ cm<sup>−

3</sup>.

7. The semiconductor device according to claim 1,

wherein said second well region is formed to include a position in plan view at which a total sum of distances between said second well region and said plurality of first well regions becomes a minimum.

8. The semiconductor device according to claim 1,

wherein said second well region is formed at a position deeper than the position of said first well regions.

9. The semiconductor device according to claim 8,

wherein said second well region is connected to said first well regions there below.

10. The semiconductor device according to claim 1,

wherein a depth of said first well regions is substantially the same as a depth of said second well region.

11. The semiconductor device according to claim 1,

wherein said first well regions and said second well region are different from each other in a distribution of an impurity concentration of the second conductivity type in the depth direction from the surface of said semiconductor layer.

12. The semiconductor device according to claim 1, further comprising on said first conductivity region, a high-concentration region higher than said first conductivity region in a first conductivity type impurity concentration.

13. The semiconductor device according to claim 12,

wherein said first conductivity type impurity concentration of said high-concentration region is in a range between 1×

10¹⁶ cm<sup>−

3</sup> and 1×

10¹⁸ cm<sup>−

3</sup>.

14. The semiconductor device according to claim 12,

wherein said high-concentration region is formed deeper than said first well regions.

15. The semiconductor device according to claim 1, further comprising

a peripheral region of the second conductivity type in said first conductivity region around a cell region including said plurality of first well regions.

16. The semiconductor device according to claim 15,

wherein an impurity concentration of the second conductivity type of said first well regions is substantially the same as an impurity concentration of the second conductivity type of said peripheral region.

17. The semiconductor device according to claim 15,

wherein a depth of said first well regions is substantially the same as a depth of said peripheral region.

18. The semiconductor device according to claim 1,

wherein said semiconductor substrate is formed of a wide bandgap semiconductor.

19. The semiconductor device according to claim 18,

wherein said wide bandgap semiconductor is a silicon carbide.

20. The semiconductor device according to claim 1,

wherein said second well region is connected to at least one of said first well regions.

21. The semiconductor device according to claim 1, further comprising:

an interlayer insulating film electrically isolating said source electrode and said gate electrode and having a source contact hole,

wherein said source electrode is electrically connected to both of said source region and a second conductivity type region in said first well region via said single source contact hole.

22. The semiconductor device according to claim 1, wherein:

said second well region includes a plurality of maximum value points, which do not vertically overlap the first well region, which are deeper than said surface of said semiconductor layer between said gate electrode and said drain electrode, and said plurality of maximum value points extend from one side of said second well region to another side of said second well region in a horizontal direction.

23. The semiconductor device according to claim 1, wherein:

the second conductivity type impurity concentration of the maximum value point is at least twenty times greater than a second conductivity type impurity concentration of the surface of said second well region.

24. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a semiconductor layer on a surface of said semiconductor substrate;

a source electrode on a surface of said semiconductor layer;

a drain electrode on a rear surface of said semiconductor substrate; and

a gate electrode forming a channel region in said semiconductor layer;

wherein said semiconductor layer comprises;

a first conductivity region on said surface of said semiconductor substrate;

a plurality of first well regions of a second conductivity type on said first conductivity region, facing said gate electrode with an insulating film therebetween;

a source region of the first conductivity type in a surface region of each of said first well regions, connected to said source electrode; and

a second well region of the second conductivity type in said semiconductor layer which is vertically overlapped by the gate electrode, the second well region of the second conductivity type in said semiconductor layer overlapping the drain electrode,

wherein a second conductivity type impurity concentration profile of said second well region includes a maximum value point, which is at a position which is not vertically overlapped by the first well region, which is deeper than a surface of said second well region between said gate electrode and said drain electrode, and

wherein a region of the first conductivity type overlies said second well region.