Trench gate trench field plate vertical MOSFET

• US 10,062,777 B2
• Filed: 04/12/2017
• Issued: 08/28/2018
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Denison, Marie, Pendharkar, Sameer, Mathur, Guru
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US15/485,892
• Publication Number:
  US 20170222040A1
• Time in Patent Office: 503 Days
• Field of Search: 257334
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Claims

1. A vertical drain extended transistor formed in a semiconductor substrate, comprising:

a first trench structure comprising;

a first trench;

a first insulating liner formed on sides and bottom of the first trench; and

a first conductive material operable to have an electrical potential and formed on the first insulating liner;

a second trench structure comprising;

a second trench;

a second insulating liner formed on sides and bottom of the second trench; and

a second conductive material operable to have said electrical potential and formed on the second insulating liner;

a gate structure comprising;

a gate trench;

a gate dielectric layer on sides and bottom of the gate trench; and

a polysilicon gate on the gate dielectric layer in the gate trench, wherein the gate structure is spaced apart from the first trench structure and the second trench structure, wherein no trench structure is located between the first trench structure and the gate structure or between the second trench structure and the gate structure;

an n-type vertically oriented drift region extending below the gate structure, wherein the first trench structure and the second trench structure are deeper than a top of the n-type vertically oriented drift layer;

a p-type body region type over the n-type vertically extended drift region, contacting the gate dielectric layer at a side of the gate trench; and

an n-type source region over the p-type body region, contacting to the gate dielectric layer at the side of the gate trench and extending to a surface of the semiconductor substrate between the first trench structure and the gate structure.

2. The vertical drain extended transistor of claim 1, wherein the first conductive material is electrically coupled to the n-type source region.

3. The vertical drain extended transistor of claim 1, wherein the semiconductor substrate includes an epitaxial layer, and the first trench structure, the second trench structure and the gate structure are formed in the epitaxial layer.

4. The vertical drain extended transistor of claim 1, wherein the first trench structure and the second trench structure are 0.5 to 1.5 microns wide.

5. The vertical drain extended transistor of claim 1, wherein the gate dielectric layer comprises silicon dioxide.

6. The vertical drain extended transistor of claim 1, wherein the gate dielectric layer is comprised of silicon dioxide and aluminum oxy-nitride.

7. The vertical drain extended transistor of claim 1, wherein the first conductive material and the second conductive material comprise polysilicon.

8. The vertical drain extended transistor of claim 1, wherein the p-type body region is a first p-type body region, the n-type source region is a first n-type source region, the n-type vertically oriented drift region is a first n-type vertically oriented drift region, and further comprising:

a second p-type body region over the vertically extended drift region, contacting the gate dielectric layer at an opposite side of the gate trench; and

a second n-type source region over the second p-type body region, contacting to the gate dielectric layer at the opposite side of the gate trench and extending to the surface of the semiconductor substrate between the second trench structure and the gate structure.

9. The vertical drain extended transistor of claim 8, wherein the gate structure is a first gate structure and further comprising:

a second gate structure;

a third trench structure comprising;

a third trench;

a third insulating liner formed on sides and bottom of the third trench; and

a third conductive material operable to have said electrical potential and formed on the third insulating liner, wherein the second gate structure is spaced apart from the second trench structure and the third trench structure;

a second n-type vertically oriented drift region;

a third p-type body region over the second n-type vertically oriented drift region, contacting one side of the second gate structure; and

a third n-type source region over the third p-type body region, contacting the one side of the second gate structure and extending to the surface of the semiconductor substrate between the third trench structure and the second gate structure,

wherein the third trench structure is deeper than a top of the second n-type vertically oriented drift region.

10. The vertical drain extended transistor of claim 9, wherein the third conductive material is electrically coupled to the third n-type source region.