Semiconductor on insulator devices containing permanent charge

• US 10,062,788 B2
• Filed: 04/28/2009
• Issued: 08/28/2018
• Est. Priority Date: 07/30/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Paul, Amit, Darwish, Mohamed N.
• Primary Examiner(s): Vu, David
• Application Number:
  US12/431,005
• Publication Number:
  US 20100025763A1
• Time in Patent Office: 3,409 Days
• Field of Search: 257343
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical

Abstract

A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too.

Claims

1. A lateral semiconductor-on-insulator device comprising:

a body region connected to a drain region by a semiconductor-on-insulator region;

a gate electrode which is capacitively coupled to said body region;

a dielectric overlying said semiconductor-on-insulator region between the body region and the drain region; and

permanent charge, embedded in said dielectric, and having a density at least sufficient to cause depletion in the semiconductor-on-insulator region;

wherein said permanent charge comprises implanted ions; and

wherein at least some of said permanent charge overlies regions which are not overlaid by the gate electrode.

2. The lateral semiconductor-on-insulator device of claim 1, further comprising

an insulator region beneath the semiconductor-on-insulator region, and

additional permanent charge embedded in the insulator region,

wherein said additional permanent charge at least partly depletes the semiconductor-on-insulator region.

3. The lateral semiconductor-on-insulator device of claim 2, further comprising a trench gate.

4. The lateral semiconductor-on-insulator device of claim 2, wherein said insulator is continuous across the entire device.

5. The lateral semiconductor-on-insulator device of claim 1, further comprising a trench gate.

6. A lateral semiconductor-on-insulator device comprising:

a body region connected to a drain region by a semiconductor-on-insulator region;

a gate electrode which is capacitively coupled to the body region;

a dielectric overlying said semiconductor-on-insulator region between the body region and the drain region; and

permanent charge, embedded in said dielectric, and having a density at least sufficient to cause depletion in the semiconductor-on-insulator region;

wherein said permanent charge has a density sufficient to cause inversion in said semiconductor-on-insulator region;

wherein at least some of said permanent charge overlies regions which are not overlaid by the gate electrode; and

wherein said permanent charge comprises implanted ions.

7. A lateral semiconductor-on-insulator device comprising:

an n-type source region, separated from a drift region by a p-type body region;

said drift region separating said body region from a drain region;

a dielectric overlying said drift region;

said drift region overlying a buried dielectric layer; and

permanent charge, embedded at the interface between said dielectric and said drift region, and having a density at least sufficient to cause depletion in the drift region;

wherein said permanent charge comprises implanted ions.

8. The lateral semiconductor-on-insulator device of claim 7, further comprising additional permanent charges embedded in said buried dielectric layer, and wherein said additional permanent charges at least partly deplete said drift region.

9. The lateral semiconductor-on-insulator device of claim 7, wherein said drift region is n-type.

10. The lateral semiconductor-on-insulator device of claim 7, wherein said drift region includes only a single conductivity type.

11. The lateral semiconductor-on-insulator device of claim 7, further comprising a trench gate which controls conduction through part of said body region.

12. The lateral semiconductor device of claim 7, further comprising a carrier source comprising a first-conductivity type source diffusion, and wherein said body is second-conductivity-type, and wherein the electrode lies within an isolation trench and is capacitively coupled to define a channel region which is interposed between said source diffusion and said drift region.

13. The semiconductor device of claim 7, wherein said drift region is overlain by a dielectric layer which also contains ones of said permanent charges.

14. The semiconductor device of claim 7, wherein said drift region is overlain by a dielectric layer which also contains ones of said permanent charges, and is also underlain by a buried dielectric layer which also contains ones of said permanent charges.

15. The semiconductor device of claim 7, further comprising a tapered isolation trench.

16. A lateral semiconductor-on-insulator device comprising:

an n-type source region, separated from a drift region by a p-type body region;

said drift region separating said body region from a drain region;

a dielectric overlying said drift region;

said drift region overlying a buried dielectric layer; and

permanent charge, embedded at the interface between said dielectric and said drift region, and having a density at least sufficient to cause depletion in the drift region;

wherein said permanent charge has a density sufficient to cause inversion in said drift region; and

wherein said permanent charge comprises implanted ions.

17. The lateral semiconductor-on-insulator device of claim 16, further comprising:

a gate electrode capacitively coupled to said body region;

wherein said permanent charge has a polarity which balances charge in nearby portions of said drift region when said drift region is depleted; and

wherein at least some of said permanent charge overlies regions which are not overlaid by the gate electrode.

18. The semiconductor device of claim 17, wherein the buried dielectric layer contains ones of said permanent charges, and the drift region is laterally confined by a dielectric trench which also contains ones of said permanent charges.

19. The lateral semiconductor device of claim 17, wherein the gate is capacitively coupled to define a channel region which is interposed between said source region and said drift region.

20. The semiconductor device of claim 17, wherein said drift region is laterally confined by a dielectric trench which also contains ones of said permanent charges.