Level shift circuit

• US 10,063,226 B2
• Filed: 03/01/2018
• Issued: 08/28/2018
• Est. Priority Date: 03/17/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Akahane, Masashi
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US15/909,955
• Publication Number:
  US 20180191340A1
• Time in Patent Office: 180 Days
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0185 using field effect transistors only
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A level shift circuit including serially-connected first resistor and first transistor and serially-connected second resistor and second transistor, a protection circuit that receives signals at a first junction between the first resistor and the first transistor and a second junction between the second resistor and the second transistor, a latch circuit receiving an output of the protection circuit, serially-connected third and fourth transistors and serially-connected fifth and sixth transistors respectively connected in parallel to the first and second resistors, a switching time detection circuit that receives the signals at the first and second junctions and detects an occurrence of switching noise, and first and second logical AND circuits that receive outputs of the switching time detection circuit and the signals at the first and second junctions, and respectively control the fourth and sixth transistors. The third and fifth transistors are controlled by an output, or an inversion thereof, of the latch circuit.

Claims

1. A level shift circuit for shifting a level of a signal and transmitting the level-shifted signal to a circuit that drives a switching element on a high side of a half-bridge circuit, the circuit being connected to two ends of a power supply respectively via a power supply line and a reference potential line, the level shift circuit comprising:

a first series circuit of a first resistor and a first transistor, the first series circuit being connected between the power supply line and a ground potential;

a second series circuit of a second resistor and a second transistor, the second series circuit being connected between the power supply line and the ground potential;

a latch malfunction protection circuit that receives a signal at a first junction between the first resistor and the first transistor, and a signal at a second junction between the second resistor and the second transistor;

a latch circuit into which an output of the latch malfunction protection circuit is inputted;

a third transistor and a fourth transistor that are connected to each other in series and are connected in parallel to the first resistor;

a fifth transistor and a sixth transistor that are connected to each other in series and are connected in parallel to the second resistor;

a switching time detection circuit that receives the signal at the first junction and the signal at the second junction and detects an occurrence of switching noise on the reference potential line;

a first logical AND circuit that receives a first output of the switching time detection circuit and the signal at the first junction, and controls the sixth transistor; and

a second logical AND circuit that receives a second output of the switching time detection circuit and the signal at the second junction, and controls the fourth transistor,

wherein the third transistor is controlled by an output signal of the latch circuit and the fifth transistor is controlled by a signal produced by logically inverting the output signal of the latch circuit.

2. The level shift circuit according to claim 1, further comprising:

a seventh transistor that is connected in parallel to the first resistor;

an eighth transistor that is connected in parallel to the second resistor; and

a logical OR circuit that receives the signal at the first junction and the signal at the second junction, and turns on the seventh transistor and the eighth transistor only when the signal at the first junction and the signal at the second junction have both fallen below an input threshold.

3. The level shift circuit according to claim 1, wherein the switching time detection circuit includes:

a first latch circuit having a set input and a reset input, the first latch circuit receiving an output of the first logical AND circuit at the reset input thereof, and an output of the second logical AND circuit at the set input thereof, and setting an inverted output thereof as the first output;

a second latch circuit having a set input and a reset input, the second latch circuit receiving the output of the second logical AND circuit at the reset input thereof, and the output of the first logical AND circuit at the set input thereof, and setting an inverted output thereof as the second output; and

a comparator that has

a first input to receive the signal at the first junction via a third resistor, and the signal at the second junction via a fourth resistor, and

a second input connected to one end of a reference power supply, of which the other end is connected to the reference potential line,

the comparator clearing the first latch circuit and the second latch circuit when a weighted average of the signal at the first junction and the signal at the second junction exceeds a potential of the reference power supply.

4. The level shift circuit according to claim 3,

wherein the first logical AND circuit includes:

a first P channel transistor having a source, a gate and a drain, the source thereof being connected to the power supply line, the gate thereof receiving the first output of the switching time detection circuit, the first P channel transistor being controlled by the first output;

a second P channel transistor having a source, a gate and a drain, a source thereof being connected to the power supply line, a gate thereof receiving the signal at the first junction, the second P channel transistor being controlled by the signal at the first junction;

a fifth resistor that is connected between the reference potential line and the drains of the first and second P channel transistors;

a third P channel transistor having a source, a gate and a drain, the source thereof being connected to the power supply line, the gate thereof being connected to a junction between the fifth resistor and the drains of the first and second P channel transistors; and

a first N channel transistor having a source, a gate and a drain, the source thereof being connected to the reference potential line, the gate thereof being connected to the gate of the third P channel transistor, the drain thereof being connected to

the drain of the third P channel transistor,

a gate of the sixth transistor,

the reset input of the first latch circuit, and

the set input of the second latch circuit; and

wherein the second logical AND circuit includes;

a fourth P channel transistor having a source, a gate and a drain, the source thereof being connected to the power supply line, the gate thereof receiving the second output of the switching time detection circuit, the fourth P channel transistor being controlled by the second output;

a fifth P channel transistor having a source, a gate and a drain, the source thereof being connected to the power supply line, the gate thereof receiving the signal at the second junction, the fifth P channel transistor being controlled by the signal at the second junction;

a sixth resistor that is connected between the reference potential line and the drains of the fourth and fifth P channel transistors;

a sixth P channel transistor having a source, a gate and a drain, the source thereof being connected to the power supply line, the gate thereof being connected to a junction between the sixth resistor and the drains of the fourth and fifth P channel transistors; and

a second N channel transistor having a source, a gate and a drain, the source thereof being connected to the reference potential line, the gate thereof being connected to the gate of the sixth P channel transistor, the drain thereof being connected to

the drain of the sixth P channel transistor,

a gate of the fourth transistor,

the set input of the first latch circuit, and

the reset input of the second latch circuit.