Transceiver for communication and method for controlling communication

• US 10,063,325 B2
• Filed: 03/03/2017
• Issued: 08/28/2018
• Est. Priority Date: 03/14/2016
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Tomita, Kazuhiro, Inui, Masuo
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US15/449,558
• Publication Number:
  US 20170264376A1
• Time in Patent Office: 543 Days
• CPC Class Codes: H04B 1/3822 specially adapted for use in vehicles H04B1/3827 takes precedence
• CPC Class Codes: H04B 15/005 Reducing noise, e.g. humm, from the supply
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4906 using binary codes
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Claims

1. A communication circuit comprising:

a timing determination module configured to detect a change of a bus signal from a first level to a second level, the bus signal generated by modulation of a timing signal and an input from a communication bus;

a delay module configured to determine a second time having a predetermined difference value from a first time, the bus signal changing from the second level to the first level at the first time;

an encoder configured to extend the length of time the bus signal is at the second level by changing a data signal to be output to the communication bus from the first level to the second level; and

a timing adjustment module configured to change the data signal to the second level at the second time.

2. The communication circuit of claim 1, wherein the delay module computes the predetermined difference value based on a frequency at which a harmonic level is reduced and a natural number.

3. The communication circuit of claim 1, further comprising:

a timing signal start detection module configured to detect a start of a change of the bus signal from the second level; and

a timing signal start determination module configured to determine the first time based on a bus signal interval of the bus signal detected by the timing signal start detection module.

4. The communication circuit of claim 1, further comprising:

a first comparator configured to compare a voltage level of the bus signal with a first reference voltage;

a second comparator configured to compare the voltage level with a second reference voltage, the second reference voltage different from the first reference voltage; and

a timing signal start determination module configured to determine a time of a start of a change of the bus signal from the second level based on a comparison of the first comparator and the second comparator.

5. The communication circuit of claim 1, wherein the delay module determines the second time after the change of the bus signal from the first level to the second level.

6. The communication circuit of claim 5, further comprising:

a first comparator configured to compare a voltage level of the bus signal with a first reference voltage;

a second comparator configured to compare the voltage level with a second reference voltage different from the first reference voltage; and

a timing signal start determination module configured to determine a time of a change of the bus signal from the first level to the second level based on a comparison result from the first comparator and the second comparator.

7. The communication circuit of claim 1, wherein the delay module determines the second time to be earlier than a start of the change from the second level of the bus signal.

8. The communication circuit of claim 1, wherein the delay module determines a time of a start of a change from the second level to the first level of the data signal to be a predetermined length of time after a timing of the change of the buss signal from the first level to the second level.

9. The communication circuit of claim 1, wherein the transceiver is included in a node used in Clock Extension Peripheral Interface (CXPI) communication.

10. The communication circuit of claim 9, wherein the transceiver functions as a slave node transceiver communicating with a master node transceiver over the communication bus.

11. A method for controlling communication by a transceiver over a communication bus, the method comprising:

detecting a change from a first level to a second level of a bus signal generated by modulation of a timing signal and an input from the communication bus;

determining a second time having a predetermined time difference from a first time, the bus signal changing from the second level to the first level at the first time;

extending the second level of the bus signal by changing the data signal to be output to the communication bus from the first level to the second level; and

changing the bus signal to the second level at the second time.

12. The method of claim 11, wherein the predetermined time difference is computed based on a frequency at which a harmonic level is reduced and a natural number.

13. The method of claim 11, further comprising:

detecting a change of the bus signal from the second level to the first level by a detector module; and

determining the first time based on a time of the change detected by the detector module.

14. The method of claim 11, wherein:

the transceiver includes a first comparator and a second comparator; and

the method further comprises;

comparing with the first comparator a voltage level of the bus signal with a first reference voltage,

comparing the voltage level with a second reference voltage with the second comparator, the second reference voltage substantially different from the first reference voltage, and

determining a time of a change of the bus signal from the second level to the first level based on a comparison result from the first comparator and the second comparator.

15. The method of claim 11, further comprising determining the second time to be after the change of the bus signal from the first level to the second level.

16. The method of claim 15, wherein:

the transceiver includes a first comparator and a second comparator; and

the method further comprises;

comparing with the first comparator a voltage level of the bus signal with a first reference voltage,

comparing with the second comparator the voltage level of the bus signal with a second reference voltage, the second reference voltage substantially different from the first reference voltage, and

determining a time of a change of the bus signal from the first level to the second level based on a comparison result from the first comparator and the second comparator.

17. The method of claim 11, further comprising determining the second time to be earlier than a time of a change of the bus signal from the second level to the first level.

18. The method of claim 11, further comprising determining a time of a start of a change of the data signal from the second level to the first level to be a predetermined length of time after the change of the bus signal from the first level to the second level.

19. The method of claim 11, wherein the transceiver is included in a node used in Clock Extension Peripheral Interface (CXPI) communication.

20. The method of claim 19, wherein the transceiver functions as a slave node transceiver communicating with a master node transceiver over the communication bus.