Optical clock recovery using feedback phase rotator with non-linear compensation

• US 10,063,367 B1
• Filed: 04/28/2017
• Issued: 08/28/2018
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Ciena Corporation
• Original Assignee: Ciena Corporation
• Inventors: Aouini, Sadok, Ben-Hamida, Naim, Kurowski, Christopher, Jakober, Lukas
• Primary Examiner(s): Wong, Linda
• Application Number:
  US15/581,676
• Time in Patent Office: 487 Days
• Field of Search: 375219, 375220, 375222, 375221, 375229-236, 375226, 375240, 37524026, 37524027, 37524028, 37524029, 375254, 375259, 375285, 375284, 375278, 375294, 375293, 375295, 375296, 375306, 375307, 375308, 375312, 375354, 375356, 375355, 375362, 375359, 375371, 375373, 375374, 375375, 375376
• CPC Class Codes: H03L 2207/00 Indexing scheme relating to automatic control of frequency or phase and to synchronisation
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/18 Temporarily disabling, deactivating or stopping the frequency counter or divider
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 10/40 Transceivers

Abstract

A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

Claims

1. A system, comprising:

a phase locked loop (PLL) device that comprises

an analog phase detector configured to obtain a reference signal, and

a voltage-controlled oscillator (VCO) device, wherein the VCO device is configured to generate, based on the reference signal, an output signal;

a phase rotator coupled to the VCO device and the analog phase detector;

a first digital phase detector coupled to the VCO device, the first digital phase detector configured to determine an amount of phase difference between a transmitter clock signal and the output signal; and

a first digital accumulator coupled to the first digital phase detector,

wherein the phase rotator and the first digital accumulator are configured, using the amount of phase difference between the transmitter clock signal and the output signal, to filter a portion of the amount of phase difference from the output signal to generate a filtered signal for transmission to the analog phase detector,

wherein the phase rotator is configured to generate an in-phase (I) phase signal and a quadrature (Q) phase signal, and

wherein the phase rotator is configured to implement a non-linear compensation scheme based on a mismatch of the I phase signal and the Q phase signal.

2. The system of claim 1, further comprising:

a lookup table circuit coupled to the first digital accumulator,

wherein the lookup table circuit is configured to generate a control signal based on a value of the amount of phase difference between the transmitter clock signal and the output signal, and

wherein the control signal is configured to produce, using the phase rotator, a predetermined phase shift in a feedback signal within the PLL device.

3. The system of claim 1, further comprising:

a delay element coupled to the phase rotator and the analog phase detector;

a second digital phase detector coupled to the delay element and the phase rotator, the second digital phase detector configured to determine an amount of PLL noise based on the reference signal and the filtered signal; and

a digital filter coupled to the second digital phase detector,

wherein the delay element and the digital filter are configured, using the amount of PLL noise, to further filter a portion of the amount of PLL noise from the filtered signal.

4. The system of claim 1, further comprising:

a reference clock source; and

a frequency counter coupled to the VCO device and the reference clock source,

wherein the frequency counter is configured to determine a frequency difference between a frequency of the reference clock source and a frequency of the VCO device, and

wherein the frequency counter is further configured to generate a control signal configured to change the frequency of the reference clock source based on the frequency difference.

5. The system of claim 1, further comprising:

a gain block coupled to the first digital phase detector; and

a varactor coupled to the VCO device and the gain block,

wherein the gain block is configured to generate a control signal configured to filter, using the varactor, a portion of an amount of PLL noise that is produced within the PLL device by the phase rotator.

6. The system of claim 1,

wherein the first digital phase detector is a Godard digital phase detector, and

wherein the transmitter clock signal is extracted from an optical signal using Godard binning.

7. The system of claim 1,

wherein the transmitter clock signal is extracted from a serializer-deserializer (SerDes) signal.

8. The system of claim 1,

wherein the phase rotator decouples a clock recovery bandwidth from a frequency of the PLL device.

9. The system of claim 1,

wherein the output signal is a receiver clock signal within an optical transceiver.

10. An apparatus, comprising:

a phased locked loop (PLL) device; and

a processing system coupled to the PLL device, wherein the processing system is configured to

obtain a first output signal from the PLL device,

determine, using a first digital phase detector, the first output signal, and a transmitter clock signal, an amount of phase difference between the first output signal and the transmitter clock signal, and

filter, using a phase rotator and a first digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal,

wherein the phase rotator is configured to generate an in-phase (I) phase signal and a quadrature (Q) phase signal, and

wherein the phase rotator is configured to implement a non-linear compensation scheme based on a mismatch of the I phase signal and the Q phase signal.

11. The apparatus of claim 10, wherein the processing system comprises:

a lookup table circuit coupled to the phase rotator,

wherein the lookup table circuit is configured to determine the portion of the amount of phase difference filtered from the output signal.

12. The apparatus of claim 10, wherein the processing system comprises:

a delay element coupled to the phase rotator and the PLL device; and

a digital filter coupled to a second digital phase detector and the delay element,

wherein the delay element and the digital filter are configured, using the amount of PLL noise, to further filter a portion of the amount of PLL noise from the filtered signal.

13. The apparatus of claim 10, further comprising:

a reference clock source,

wherein the processing system is further configured to determine a frequency difference between a frequency of a reference clock source and a frequency of the VCO device, and

wherein the processing system is further configured to change the frequency of the reference clock source based on the frequency difference.

14. The apparatus of claim 10, further comprising:

a varactor coupled to the VCO device,

wherein the processing system is further configured to filter, using the varactor, a portion of an amount of PLL noise that is produced within the PLL device by the phase rotator.

15. The apparatus of claim 10,

wherein the first digital phase detector is a Godard digital phase detector, and

wherein the transmitter clock signal is extracted from an optical signal using Godard binning.

16. The apparatus of claim 10,

wherein the transmitter clock signal is extracted from a serializer-deserializer (SerDes) system.

17. The apparatus of claim 10,

wherein the phase rotator decouples a clock recovery bandwidth from a frequency of a voltage-controlled oscillator (VCO) device in the PLL device.

18. A method for clock recovery, comprising:

obtaining an output signal from a phase locked loop (PLL) device;

determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal, and

filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal,

wherein the phase rotator is configured to generate an in-phase (I) phase signal and a quadrature (Q) phase signal, and

wherein the phase rotator is configured to implement a non-linear compensation scheme based on a mismatch of the I phase signal and the Q phase signal.