Method and device for checking an identifier

• US 10,063,370 B2
• Filed: 09/11/2014
• Issued: 08/28/2018
• Est. Priority Date: 09/11/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Temple, Christopher, Nugraha, Dian Tresna, Wiley, Edward, Heidt, Laurent
• Primary Examiner(s): Homayounmehr, Farid
• Assistant Examiner(s): Zhu, Zhimei
• Application Number:
  US14/483,716
• Publication Number:
  US 20160080376A1
• Time in Patent Office: 1,447 Days
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system
• CPC Class Codes: H04L 2209/26 Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
• CPC Class Codes: H04L 9/3234 involving additional secure or trusted devices, e.g. TPM, smartcard, USB or software token network architectures or network communication protocols for supporting authentication of entities using an additional device in a packet data network H04L63/0853

Abstract

An embodiment relates to a method for processing data that includes (a) calculating a second identifier based on input data, (b) conducting a first operation comparing the second identifier with a first identifier, and (c) conducting a second operation comparing the second identifier with a modified first identifier.

Claims

1. A method for processing data in a security processor comprising:

receiving, at the security processor, input data and a first identifier from a master processor;

calculating a second identifier based on the input data using the security processor;

conducting a first operation comparing the second identifier with the first identifier using the security processor;

receiving, at the security processor, a modified first identifier from the master processor, wherein the modified first identifier is obtained via at least one logical operation applied on the first identifier using the master processor, and wherein the modified first identifier is different from the first identifier;

conducting a second operation comparing the second identifier with the modified first identifier using the security processor; and

providing, using the security processor, a result of the first operation and a result of the second operation to the master processor;

wherein the first identifier is verified successfully when the first identifier matches the second identifier and the first operation and the second operation provide different results; and

wherein the first identifier is not verified successfully when the first operation and the second operation provide the same results.

2. The method according to claim 1, further comprising:

receiving at the security processor the input data, the first identifier, a length of the first identifier and a key information from a master processor, then

calculating the second identifier based on the input data and also with the key information using the security processor; and

conducting the first operation using the security processor by bit-wise comparing the second identifier with the first identifier using the length of the first identifier.

3. The method according to claim 1, further comprising receiving at the security processor the modified first identifier and a length of the modified first identifier from the master processor, and then

conducting at the security processor the second operation by bit-wise comparing the second identifier with the modified first identifier using the length of the modified first identifier.

4. The method according to claim 1, wherein the modified first identifier is a bit-wise inversion of the first identifier.

5. The method according to claim 1, wherein the first identifier and the second identifier are based on a hash function, in particular on a cryptographic hash function.

6. The method according to claim 1,

wherein the first operation comprises an EXOR operation based on the bits of the first identifier and the bits of the second identifier,

wherein for each bit of the first identifier a result of the bit-wise EXOR operation is inverted and AND-linked with a previous result, wherein

the previous result is logical “

1”

in case at least one previous comparison indicated identity between bits of the first identifier and the second identifier or in case no bits have been compared before and

the previous result is logical “

0”

in case at least one previous comparison indicated a discrepancy between bits of the first identifier and the second identifier.

7. The method according to claim 1,

wherein the second operation comprises an EXOR operation based on the bits of the modified first identifier and the bits of the second identifier,

wherein for each bit of the modified first identifier a result of the bit-wise EXOR operation is inverted and OR-linked with a previous result, wherein

the previous result is logical “

1”

in case at least one previous comparison indicated identity between bits of the modified first identifier and the second identifier and

the previous result is logical “

0”

in case at least one previous comparison indicated a discrepancy between bits of the modified first identifier and the second identifier or in case no bits have been compared before.

8. A non-transitory computer readable medium containing instructions thereon that are directly loadable into a memory of a digital processing device, comprising software code portions for performing the steps of the method according to claim 1.

9. A device for checking a first identifier, comprising a processing unit that is configured to

convey the first identifier and input data to a security processor,

convey a modified first identifier to the security processor, wherein the modified first identifier is obtained via at least one logical operation applied on the first identifier using the processing unit, and wherein the modified first identifier is different from the first identifier;

obtain a first result of a first operation conducted by the security processor and a second result of a second operation conducted by the security processor;

wherein the first operation compares the first identifier with a second identifier calculated by the security processor from the input data and wherein the second operation compares the second identifier with the modified first identifier; and

assess the first result and the second result;

wherein the first identifier is verified successfully when the first identifier matches the second identifier and the first operation and the second operation provide different results; and

wherein the first identifier is not verified successfully when the first operation and the second operation provide the same results.

10. The device according to claim 9, wherein in assessing the first result and the second result the processing unit is further configured to initiate a predefined action based on the successfully verified first identifier in case the first result and the second result are different.

11. The device according to claim 9, wherein the modified first identifier is a bit-wise inversion of the first identifier.

12. The device according to claim 9, wherein the first identifier is obtained from an external component.

13. The device according to claim 9, wherein the processing unit is further configured to

convey a length of the first identifier to the security processor,

convey a length of the modified first identifier to the security processor,

obtain the first result of the first operation and the second result of the second operation conducted by the security processor using the length of the first modified first identifier.

14. A device for processing data, comprising a processing unit that is configured to

obtain a first identifier and input data from a master processor;

calculate a second identifier based on the input data;

conduct a first operation comparing the second identifier with the first identifier;

obtain a modified first identifier from the master processor, wherein the modified first identifier is obtained via at least one logical operation applied on the first identifier using the master processor and wherein the modified first identifier is different from the first identifier;

conduct a second operation comparing the second identifier with the modified first identifier; and

convey a result of the first operation and a result of the second operation to the master processor;

wherein the first identifier is verified successfully when the first identifier matches the second identifier and the first operation and the second operation provide different results; and

wherein the first identifier is not verified successfully when the first operation and the second operation provide the same results.

15. The device according to claim 14, wherein the processing unit is further configured to

receive the input data, the first identifier, a length of the first identifier and a key information from the master processor;

calculate the second identifier based on the input data and the key information;

conduct the first operation by bit-wise comparing the second identifier with the first identifier using the length of the first identifier;

receive the modified first identifier and a length of the modified first identifier from the master processor; and

conduct the second operation by bit-wise comparing the second identifier with the modified first identifier using the length of the modified first identifier.

16. The device according to claim 14, wherein the modified first identifier is a bit-wise inversion of the first identifier.

17. A device for processing data, comprising a processing unit, comprising:

means for obtaining a first identifier and input data from a master processor;

means for calculating a second identifier based on the input data;

means for conducting a first operation comparing the second identifier with the first identifier;

means for obtaining a modified first identifier from the master processor, wherein the modified first identifier is obtained via at least one logical operation applied on the first identifier using the master processor and wherein the modified first identifier is different from the first identifier;

means for conducting a second operation comparing the second identifier with the modified first identifier; and

means for conveying a result of the first operation and a result of the second operation to the master processor;

wherein the first identifier is verified successfully when the first identifier matches the second identifier and the first operation and the second operation provide different results; and

wherein the first identifier is not verified successfully when the first operation and the second operation provide the same results.